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| 型號(hào)： | AC164336 |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 125/285頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MODULE SOCKET FOR PM3 28/44QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 模塊/板類型： | QFN 插口模塊 |
| 適用于相關(guān)產(chǎn)品： | MPLAB? PM3 |
| 產(chǎn)品目錄頁(yè)面： | 658 (CN2011-ZH PDF) |
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dsPIC30F1010/202X
DS70178C-page 208
Preliminary
2006 Microchip Technology Inc.
18.6
INTERNAL FAST RC OSCILLATOR
(FRC)
FRC is a fast, precise frequency internal RC oscillator.
The FRC oscillator is designed to run at a frequency of
6.4/9.7/14.55 MHz (<±2% accuracy). The FRC oscilla-
tor option is intended to be accurate enough to provide
the clock frequency necessary to maintain baud rate
tolerance for serial data transmissions. The user has
the ability to tune the FRC frequency by +-3%.
The FRC oscillator is powered:
a)
Any time the EC or HS Oscillator modes are
NOT selected.
b)
When the fail-safe clock monitor is enabled and
a clock fail is detected, forcing a switch to FRC.
18.6.1
FREQUENCY RANGE SELECTION
The FRC module has a “Gear Shift” control signal that
selects low range (9.7 MHz for industrial temperature
rated parts and 6.4 MHz for extended temperature
rated parts) or high range (14.55 MHz for industrial
temperture rated parts and 9.7 MHz for extended tem-
perature rated parts) frequency of operation. This fea-
ture enables a dsPIC DSC device to operate up to a
maiximum speed of 20 MIPS at 3.3V or up to a maxi-
mum speed of 30 MIPS at 5.0V and remain with
system specifications.
18.6.2
NOMINAL FREQUENCY VALUES
The FRC module is calibrated to a nominal 9.7 MHz
for industrial temperature rated parts and 6.4 MHz for
extended temperature rated parts in low range and
14.55 MHz for industrial temperture rated parts and
9.7 MHz for extended temperature rated parts in high
range This feature enables a user to “tune” the dsPIC
DSC device frequency of operation by +-3% and still
remain within system specifications.
18.6.3
FRC FREQUENCY USER TUNING
The FRC is calibrated at the factory to give a nominal
6.4/9.7/14.55 MHz. The TUN<3:0> field in the OSC-
TUN register is available to the user for trimming the
FRC oscillator frequency in applications.
The 4-bit tuning control signals are supplied by the
OSCTUN or the OSCTUN2 registers depending on
the TSEQEN bit in the OSCCON register.
The tuning range of the 14.55 MHz oscillator is
±0.45 MHz (±3%) nominal.
The base frequency can be tuned in the user's appli-
cation. This frequency tuning capability allows the user
to deviate from the factory calibrated frequency. The
user can tune the frequency by writing to the OSCTUN
register TUN<3:0> bits.
18.6.4
CLOCK DITHERING LOGIC
In power conversion applications, the primary electri-
cal noise emission that the designers want to reduce is
caused by the power transistors switching at the PWM
frequency. By changing the system clock frequency of
the SMPS dsPIC DSC, the resultant PWM frequency
will change and the peak EMI will be reduced at the
noise is spread over a wider frequency range.
Typically, the range of frequency variation is few
percent. The dsPIC30F1010/202X can provide two
ways to vary system clock frequency on a PWM cycle
basis. These are Frequency Sequencing mode and
Pseudo Random Clock Dithering mode. Table 18-8
shows the implementation details of both these
methods.
18.6.5
FREQUENCY SEQUENCING MODE
The Frequency Sequencing mode enables the PWM
module to select a sequence of eight different FRC
TUN values to vary the system frequency with each
rollover of the primary PWM time base. The OSCTUN
and the OSCTUN2 registers allow the user to specify
eight sequential tune values if the TSEQEN bit is set in
the OSCCON register. If the TSEQEN bit is zero, then
only the TUN bits affect the FRC frequency.
A 4-bit wide multiplexer with eight sets of inputs
selects the tuning value from the TUN and the TSEQx
bit fields. The multiplexer is controlled by the
ROLL<5:3>
counter
in
the
PWM
module.
The
ROLL<5:3> counter increments every time the primary
time base rolls over after reaching the period value.
18.6.6
PSEUDO RANDOM CLOCK
DITHERING MODE
The Pseudo Random Clock Dither (PRCD) logic is
implemented with a 15-bit LFSR (Linear Feedback
Shift Register), which is a shift register with a few
exclusive OR gates. The lower four bits of the LFSR
provides the FRC TUNE bits. The PRCD feature is
enabled by setting the PRCDEN bit in the OSCCON
register. The LSFR is “clocked” (enabled to clock)
once every time the ROLL<3> bit changes state,
which occurs once every 8 PWM cycles.
18.6.7
FAIL-SAFE CLOCK MONITOR
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM Configuration bits (Clock
Switch and Monitor Selection bits) in the FOSC
Configuration register.
In the event of an oscillator failure, the FSCM will
generate a clock failure trap event and will switch the
system clock over to the FRC oscillator. The user will
then have the option to either attempt to restart the
oscillator or execute a controlled shutdown. The user
may decide to treat the trap as a warm Reset by sim-
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