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| 型號： | AC164336 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 235/285頁 |
| 文件大?。?/td> | 0K |
| 描述： | MODULE SOCKET FOR PM3 28/44QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 模塊/板類型： | QFN 插口模塊 |
| 適用于相關(guān)產(chǎn)品： | MPLAB? PM3 |
| 產(chǎn)品目錄頁面： | 658 (CN2011-ZH PDF) |
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2006 Microchip Technology Inc.
Preliminary
DS70178C-page 51
dsPIC30F1010/202X
5.4
Interrupt Sequence
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current Program
Counter and the low byte of the processor STATUS
Register (SRL), as shown in Figure 5-2. The low byte
of the STATUS register contains the processor priority
level at the time, prior to the beginning of the interrupt
cycle. The processor then loads the priority level for
this interrupt into the STATUS register. This action will
disable all lower priority interrupts until the completion
of the Interrupt Service Routine (ISR).
FIGURE 5-2:
INTERRUPT STACK
FRAME
The RETFIE (Return from Interrupt) instruction will
unstack the Program Counter and status registers to
return the processor to its state prior to the interrupt
sequence.
5.5
Alternate Vector Table
In Program Memory, the IVT is followed by the AIVT, as
shown in Figure 5-1. Access to the Alternate Vector
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and excep-
tion processes will use the alternate vectors instead of
the default vectors. The alternate vectors are organized
in the same manner as the default vectors. The AIVT
supports emulation and debugging efforts by providing
a means to switch between an application and a sup-
port environment, without requiring the interrupt vec-
tors to be reprogrammed. This feature also enables
switching between applications for evaluation of
different software algorithms at run time.
If the AIVT is not required, the program memory allo-
cated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6
Fast Context Saving
A context saving option is available using shadow reg-
isters. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S
instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S
instructions for fast context saving, then a
higher priority ISR should not include the same instruc-
tions. Users must save the key registers in software
during a lower priority interrupt, if the higher priority ISR
uses fast context saving.
5.7
External Interrupt Requests
The interrupt controller supports three external inter-
rupt request signals, INT0-INT2. These inputs are edge
sensitive; they require a low-to-high or a high-to-low
transition to generate an interrupt request. The
INTCON2 register has three bits, INT0EP-INT2EP, that
select the polarity of the edge detection circuitry.
5.8
Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine needed to process the interrupt request.
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON<3>) is always
clear when interrupts are being pro-
cessed. It is set only during execution of
traps.
<Free Word>
0
15
W15 (before CALL)
W15 (after CALL)
S
tack
G
row
s
T
o
w
a
rd
s
H
ig
her
Addre
s
PUSH : [W15++]
POP
: [--W15]
0x0000
PC<15:0>
SRL IPL3 PC<22:16>
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AC164337 | 功能描述:插座和適配器 PM3 40L SOCKET MODULE RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| AC164338 | 功能描述:插座和適配器 PM3 Socket Module RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| AC164339 | 功能描述:插座和適配器 MPLAB PM3 Socket Module RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| AC164340 | 功能描述:插座和適配器 MPLAB PM3 Socket Mod for 8LDFN or 20LQFN RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
| AC164341 | 功能描述:插座和適配器 MPLAB PM3 Socket Mod for 16l QFN RoHS:否 制造商:Silicon Labs 產(chǎn)品:Adapter 用于:EM35x |
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