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參數(shù)資料
| 型號(hào)： | A48P4616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 330PF 50V CERAMIC MONO 5% |
| 中文描述： | 16米x 16位DDR內(nèi)存 |
| 文件頁(yè)數(shù)： | 57/71頁(yè) |
| 文件大?。?/td> | 2068K |
| 代理商： | A48P4616 |
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A48P4616
Preliminary (September, 2005, Version 0.0)
56
AMIC Technology, Corp.
Electrical Characteristics & AC Timing - Absolute Specifications (continued)
(0 °C
≤
TA
≤
70
°
C; VDD = VDDQ = 2.5V
±
0.2V (DDR333); VDD = VDDQ = 2.6V
±
0.1V (DDR400), See AC Characteristics)
DDR333
6K
Min
DDR400
5T
Min
Symbol
Parameter
Max
Max
Unit
Note
t
IH
Address and control input hold time
(slow slew rate)
Address and control input setup time
(slow slew rate)
Read preamble
Read postamble
Active to Precharge
Active to Active/Auto-refresh command period
Auto-refresh
to
Active/Auto-refresh
period
Active to Read or write dalay
0.8
0.65
ns
2-4,10,11,
12,14
t
IH
0.8
0.65
ns
2-4,10,11,
12,14
1-4
1-4
1-4
1-4
t
RPRE
t
RPST
t
RAS
t
RC
0.9
0.40
40
60
1.1
0.60
70K
0.9
2.0
42
55
1.1
0.6
70K
t
CK
t
CK
ns
ns
t
RFC
command
72
70
t
CK
1-4
t
RCD
18
min
15
min
t
CK
1-4
t
RAP
Active to read command with Autoprecharge
(t
RCD
, t
RAS
)
18
12
15
-
1
6
75
200
(t
RCD
, t
RAS
)
15
10
15
-
2
6
75
200
t
CK
1-4
t
RP
t
RRD
t
WR
t
DAL
t
WTR
t
PDEX
t
XSNR
t
XSRD
t
REFI
Precharge command period
Active bank A to Active bank B command
Write vecovery time
Auto precharge write recovery + precharge time
Intemal write to read command delay
Power down exit time
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
t
CK
t
CK
t
CK
t
CK
t
CK
ns
t
CK
t
CK
μ
s
1-4
1-4
1-4
1-4,13
1-4
1-4
1-4
1-4
1-4,8
7.8
7.8
Notes:
1. Input slew rate = 1V/ns.
2. The CK/
CK
input reference level (for timing reference to CK/
CK
) is the point at which CK and
CK
cross; the input reference
level for signals other than CK/
CK
is V
REF
.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to
a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from high to low at this time, depending on t
DQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate
≥
1.0V/ns. Slew rate is measured between V
OH (AC)
and V
OL (AC)
.
10. For command/address input slew rate
≥
0.5V/ns and < 1.0V/ns. Slew rate is measured between V
OH (AC)
and V
OL (AC)
.
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