參數(shù)資料
型號： A48P4616
廠商： AMIC Technology Corporation
英文描述： CAP 330PF 50V CERAMIC MONO 5%
中文描述： 16米x 16位DDR內(nèi)存
文件頁數(shù)： 56/71頁
文件大?。?/td> 2068K
代理商： A48P4616
A48P4616
Preliminary (September, 2005, Version 0.0)
55
AMIC Technology, Corp.
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C
≤
TA
≤
70
°
C; VDD = VDDQ = 2.5V
±
0.2V (DDR333); VDD = VDDQ = 2.6V
±
0.1V (DDR400), See AC Characteristics)
DDR333 (6K)
DDR400 (5T)
Symbol
Parameter
Min
Max
Min
Max
Unit
Note
t
AC
DQ output access time from CK/
CK
-0.70
+0.70
-0.65
+0.65
ns
1-4
t
DQSCK
DQS output access time from CK/
CK
-0.60
+0.60
-0.55
+0.55
ns
1-4
t
CH
CK high-level width
0.45
0.55
0.45
0.55
t
CK
1-4
t
CL
CK low-level width
0.45
0.55
0.45
0.55
t
CK
1-4
CL = 2
7.5
12
-
-
CL = 2.5
6
12
6
12
t
CK
Clock cycle time
CL = 3
-
-
5
8
ns
1-4
t
DH
DQ and DM input hold time
0.45
0.40
ns
1-4, 15, 16
t
DS
DQ and DM input setup time
0.45
0.40
ns
1-4, 15, 16
t
IPW
Input pulse width
2.2
2.2
ns
2-4,12
t
DIPW
DQ and DM input pulse width (each input)
1.75
1.75
ns
1-4
t
HZ
Data-out high-impedance time from CK/
CK
-0.7
+0.7
-0.65
+0.65
ns
1-4,5
t
LZ
Data-out low-impedance time from CK/
CK
-0.7
+0.7
-0.65
+0.65
ns
1-4,5
t
DQSQ
DQS-DQ skew
(DQS & associated DQ signals)
TSOP Package
+0.45
+0.40
ns
1-4
t
HP
Minimum half clk period for any given cycle;
Defined by clk high (t
CH
) or low (t
CL
) time.
min
t
CL
, t
CH
min
t
CL
, t
CH
t
CK
1-4
t
QH
Data output hold time from DQS
t
HP
, t
QHS
t
HP
, t
QHS
t
CK
1-4
t
QHS
Data hold Skew Factor
TSOP Package
0.55
0.5
t
CK
1-4
t
DQSS
Write command to 1st DQS latching transition
0.75
1.25
0.72
1.25
t
CK
1-4
t
DQSH
DQS input high pulse width (write cycle)
0.35
0.35
t
CK
1-4
t
DQSL
DQS input low pulse width (write cycle)
0.35
0.35
t
CK
1-4
t
DSS
DQS falling edge to CK setup time (write cycle)
0.2
0.2
t
CK
1-4
t
DSH
DQS falling edge hold time from CK (write cycle)
0.2
0.2
t
CK
1-4
t
MRD
Mode register set command cycle time
12
12
t
CK
1-4
t
WPRES
Write preamble setup time
0
0
t
CK
1-4,7
t
WPST
Write postamble
0.40
0.60
0.40
0.60
t
CK
1-4,6
t
WPRE
Write postamble
0.25
0.25
t
CK
1-4
t
IH
Address and control input hold time (fast slew rate)
0.75
0.6
ns
2-4,9,11,12
t
IS
Address and control input hold time (fast slew rate)
0.75
0.6
ns
2-4,9,11,12
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