- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375142 > A48P4616 (AMIC Technology Corporation) CAP 330PF 50V CERAMIC MONO 5% PDF資料下載
參數(shù)資料
| 型號： | A48P4616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 330PF 50V CERAMIC MONO 5% |
| 中文描述： | 16米x 16位DDR內(nèi)存 |
| 文件頁數(shù)： | 2/71頁 |
| 文件大?。?/td> | 2068K |
| 代理商： | A48P4616 |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
A48P4616
Preliminary (September, 2005, Version 0.0)
1
AMIC Technology, Corp.
Features
CAS Latency and Frequency
Maximum Operating Frequency (MHz)
CAS
Latency
DDR400 (5T)
DDR333 (6K)
2
-
133
2.5
166
166
3
200
-
DDR 256M bit, die C, based on 110nm design rules.
Double data rate architecture: two data transfers per
clock cycle.
Bidirectional data strobe (DQ
S
) is transmitted and
received with data, to be used in capturing data at the
receiver.
DQ
S
is edge-aligned with data for reads and is center-
aligned with data for writes.
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation.
Data mask (DM) for write data.
DLL aligns DQ and DQ
S
transitions with CK transitions.
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQ
S
.
Burst lengths: 2, 4, or 8
CAS Latency: 2/2.5(DDR333), 2.5/3(DDR400)
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8μs Maximum Average Periodic Refresh Interval
2.5V (SSTL_2 compatible) I/O
V
DD
= V
DDQ
= 2.5V ± 0.2V (DDR333)
V
DD
= V
DDQ
= 2.6V ± 0.1V (DDR400)
Available in Halogen and Lead Free packaging
General Description
The 256Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQ
S
) is transmitted externally,
along with data, for use in data capture at the receiver. DQ
S
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQ
S
is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQ
S
, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class
II com-patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A49FL004TX-33F | 4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory |
| A49FL004 | 4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory |
| A49FL004TL-33 | 4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory |
| A49FL004TL-33F | 4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory |
| A49FL004TX-33 | 4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A48P48 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 44.00x44.00 fits 48.00x4 White, fits 48x48, Steel |
| A-48P48 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 44.00x44.00 fits 48.00x4 |
| A48P48G | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel, 44.00X44.00 , fits 48x48, Steel |
| A48PL | 功能描述:ANT TWO-WAY 48MHZ PL CONN RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:- 標準包裝:1 系列:* |
| A48R3612HCR | 制造商:Pentair Technical Products / Hoffman 功能描述:Type 3R Enclosure, Hng Cover |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。