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參數(shù)資料
| 型號(hào)： | A48P4616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 330PF 50V CERAMIC MONO 5% |
| 中文描述： | 16米x 16位DDR內(nèi)存 |
| 文件頁數(shù)： | 10/71頁 |
| 文件大?。?/td> | 2068K |
| 代理商： | A48P4616 |
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A48P4616
Preliminary (September, 2005, Version 0.0)
9
AMIC Technology, Corp.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3.
The ordering of accesses within a burst is determined by the
burst length, the burst type and the starting column address,
as shown in
Burst Definition
on page 10.
Read Latency
The Read latency, or CAS latency, is the delay, in clock
cycles, between the registration of a Read command and the
availability of the first burst of output data. The latency can
be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the
latency is
m
clocks, the data is available nominally coincident
with clock edge
n +
m.
Reserved states should not be used as unknown operation
or
incompatibility
with
future
versions
may
result.
Burst Definition
Starting Column Address
A1
Order of Accesses Within a Burst
Type = Sequential
0-1
Burst Length
A2
A0
0
Type = Interleaved
0-1
2
1
0
1-0
1-0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
1
0
1
2-3-0-1
3-0-1-2
2-3-0-1
3-2-1-0
4
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
0
1
1
0
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
1
0
0
0
1
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
8
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Note:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
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