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參數(shù)資料
| 型號： | A48P4616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 330PF 50V CERAMIC MONO 5% |
| 中文描述： | 16米x 16位DDR內(nèi)存 |
| 文件頁數(shù)： | 55/71頁 |
| 文件大?。?/td> | 2068K |
| 代理商： | A48P4616 |
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A48P4616
Preliminary (September, 2005, Version 0.0)
54
AMIC Technology, Corp.
AC Input Operating Conditions
(0 °C
≤
T
A
≤
70
°
C
;
V
DD
= V
DDQ
= 2.5V
±
0.2V (DDR333); V
DD
= V
DDQ
= 2.6V
±
0.1V (DDR400), See AC Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Note
V
IH (AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
V
REF
+ 0.31
V
1, 2
V
IL (AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
V
REF
– 0.31
V
1, 2
V
ID (AC)
Input Differential Voltage, CK and
CK
Inputs
0.7
V
DDQ
+ 0.6
V
1, 2, 3
V
IX (AC)
Input Crossing Point Voltage, CK and
CK
Inputs
0.5*V
DDQ
– 0.2
0.5* V
DDQ
+ 0.2
V
1, 2, 4
Notes:
1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until V
REF
stabilizes.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on
CK
.
4. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of
the same.
I
DD
Specifications and Conditions
(0 °C
≤
T
A
≤
70
°
C
;
V
DD
= V
DDQ
= 2.5V
±
0.2V(DDR333); V
DD
= V
DDQ
= 2.6V
±
0.1V (DDR400), See AC Characteristics)
Symbol
Parameter/Condition
DDR333 (6K)
tCK = 6ns
DDR333
(6KL)
tCK = 6ns
DDR400 (5T)
tCK = 5.0ns
Unit
Note
I
DD0
Operating Current
: One bank; active / precharge; t
RC
= t
RC (min)
;
DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current
: One bank; active / read / precharge; Burst =
2; t
RC
= t
RC (min)
; CL = 2.5; I
OUT
= 0mA; address and control inputs
changing once per clock cycle
Precharge Power Down Standby Current
: All banks idle;
Power Down mode; CKE
≤
V
IL (max)
Idle Standby Current:
CS
≥
V
IH (min)
; all banks idle; CKE
≥
V
IH
(min)
; address and control inputs changing once per clock cycle
Active Power Down Standby Current
: one bank active; Power
Down mode; CKE
≤
V
IL (max)
Active Standby Current
: One bank; active / precharge;
CS
≥
V
IH (min)
; CKE
≥
V
IH (min)
; t
RC
= t
RAS (max)
; DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current:
One bank; Burst = 2; reads; continuous
burst; address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
I
OUT
= 0mA
Operating Current
: One bank; Burst = 2; writes; continuous
burst; address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL = 2.5
Auto-Refresh Current
: t
RC
= t
RFC (min)
68
68
76
mA
1
I
DD1
72
72
79
mA
1
I
DD2P
4
4
4
mA
1
I
DD2N
25
25
29
mA
1
I
DD3P
10
10
11
mA
1
I
DD3N
39
39
46
mA
1
I
DD4R
87
87
105
mA
1
I
DD4W
98
98
119
mA
1
I
DD5
118
118
124
mA
1
I
DD6
Self-Refresh Current
: CKE
≤
0.2V
Operating curren
t: Four bank; four bank interleaving with BL =
4, address and control inputs randomly changing; 50% of data
changing at every transfer; t
RC
= t
RC (min)
; I
OUT
= 0mA.
2
1.5
2
mA
1.2
I
DD7
207
207
246
mA
1
Notes:
1. I
DD
specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
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