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參數(shù)資料
| 型號(hào)： | A48P4616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 330PF 50V CERAMIC MONO 5% |
| 中文描述： | 16米x 16位DDR內(nèi)存 |
| 文件頁(yè)數(shù)： | 44/71頁(yè) |
| 文件大?。?/td> | 2068K |
| 代理商： | A48P4616 |
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A48P4616
Preliminary (September, 2005, Version 0.0)
43
AMIC Technology, Corp.
Truth Table 2: Clock Enble(CKE)
CKE n-1
Previous Cycle Previous Cycle
L
L
CKE n
Current
Command n
Action n
Note
Self Refresh
Self Refresh
L
H
X
Deselect or NOP
Maintain Self-Refresh
Exit Self-Refresh
1
Power Down
L
L
X
Maintain Power Down
Power Down
All Banks Idle
L
H
H
L
Deselect or NOP
Deselect or NOP
Exit Power Down
Precharge Power Down Entry
All Banks Idle
H
L
Auto Refresh
Self Refresh Entry
Bank(s) Active
H
L
Deselect or NOP
See “Truth Table 3: Current State
Bank n - Command to Bank n
(Same Bank)” on page 44
Active Power Down Entry
H
H
Note:
1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and action n is a result of command n.
4. All states and sequences not shown are illegal or reserved.
5. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t
XSNR
) period. A
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
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