- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗4430 > A1020B-1VQ80C (Microsemi SoC)IC FPGA 2K GATES 80-VQFP COM PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | A1020B-1VQ80C |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 9/98闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 2K GATES 80-VQFP COM |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | ACT™ 1 |
| LAB/CLB鏁�(sh霉)锛� | 547 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 69 |
| 闁€(m茅n)鏁�(sh霉)锛� | 2000 |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 80-VQFP锛�14x14锛� |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)鐣�(d膩ng)鍓嶇9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)
17
Hi R e l F P GA s
1 200 XL T i m i ng Mo de l *
*Values shown for A1280XL鈥�1 at worst-case military conditions.
Input module predicted routing delay.
Output Delays
Internal Delays
Input Delays
tINH = 0.0 ns
tINSU = 0.4 ns
I/O Module
D
Q
tINGL = 3.7 ns
tINYL = 1.7 ns t
IRD2 = 5.2 ns
Combinatorial
Logic Module
tPD = 3.7 ns
Sequential
Logic Module
I/O Module
tRD1 = 1.7 ns
tDLH = 6.6 ns
I/O Module
ARRAY
CLOCKS
FMAX = 110 MHz
Combin-
atorial
Logic
in tSUD
D
Q
D
Q
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 5.9 ns
tDLH = 6.6 ns
tENHZ = 7.5 ns
tRD1 = 1.7 ns
tCO = 3.7 ns
tSU = 0.4 ns
tHD = 0.0 ns
tRD4 = 3.7 ns
Predicted
Routing
Delays
tCKH = 7.1 ns
G
FO = 256
tRD2 = 2.5 ns
tLCO = 10.7 ns (64 loads, pad-pad)
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A10V20B-VQ80C | IC FPGA 2K GATES 80-VQFP COM |
| A1020B-1VQG80C | IC FPGA 2K GATES 80-VQFP COM |
| FMC17DRYI-S734 | CONN EDGECARD 34POS DIP .100 SLD |
| ESC65DRYS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
| RSC31DTES | CONN EDGECARD 62POS .100 EYELET |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A1020B-1VQ80I | 鍔熻兘鎻忚堪:IC FPGA 2K GATES 80-VQFP IND RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛� 绯诲垪:ACT™ 1 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€(m茅n)鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛� |
| A1020B-1VQ84B | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1020B-1VQ84C | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1020B-1VQ84I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1020B-1VQ84M | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
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