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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A1020B-1VQ80C |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 18/98闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 2K GATES 80-VQFP COM |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | ACT™ 1 |
| LAB/CLB鏁�(sh霉)锛� | 547 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 69 |
| 闁€鏁�(sh霉)锛� | 2000 |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 80-VQFP锛�14x14锛� |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�鐣跺墠绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�
25
Hi R e l F P GA s
AC T 1 T i m i ng C har a c t e r i st i c s
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
Single Module
4.7
5.5
ns
tPD2
Dual Module Macros
10.8
12.7
ns
tCO
Sequential Clk to Q
4.7
5.5
ns
tGO
Latch G to Q
4.7
5.5
ns
tRS
Flip-Flop (Latch) Reset to Q
4.7
5.5
ns
Logic Module Predicted Routing Delays1
tRD1
FO=1 Routing Delay
1.5
1.7
ns
tRD2
FO=2 Routing Delay
2.3
2.7
ns
tRD3
FO=3 Routing Delay
3.4
4.0
ns
tRD4
FO=4 Routing Delay
5.0
5.9
ns
tRD8
FO=8 Routing Delay
10.6
12.5
ns
Logic Module Sequential Timing 2
tSUD
Flip-Flop (Latch) Data Input Setup
8.8
10.4
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
8.8
10.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
10.9
12.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
10.9
12.9
ns
tA
Flip-Flop Clock Input Period
23.2
27.3
ns
fMAX
Flip-Flop (Latch) Clock
Frequency
44
37
MHz
Input Module Propagation Delays
tINYH
Pad to Y High
4.9
5.8
ns
tINYL
Pad to Y Low
4.9
5.8
ns
Input Module Predicted Routing Delays1, 3
tIRD1
FO=1 Routing Delay
1.5
1.7
ns
tIRD2
FO=2 Routing Delay
2.3
2.7
ns
tIRD3
FO=3 Routing Delay
3.4
4.0
ns
tIRD4
FO=4 Routing Delay
5.0
5.9
ns
tIRD8
FO=8 Routing Delay
10.6
12.5
ns
Notes:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
2.
Setup times assume fanout of 3. Further derating information can be obtained from the DirectTime Analyzer utility.
3.
Optimization techniques may further reduce delays by 0 to 4 ns.
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
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| ESC65DRYS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
| RSC31DTES | CONN EDGECARD 62POS .100 EYELET |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A1020B-1VQ80I | 鍔熻兘鎻忚堪:IC FPGA 2K GATES 80-VQFP IND RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 鐢㈠搧鍩硅〒妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢㈠搧:Cyclone? IV FPGAs 妯欐簴鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�:6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FBGA锛�23x23锛� |
| A1020B-1VQ84B | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1020B-1VQ84C | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1020B-1VQ84I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A1020B-1VQ84M | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
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