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參數(shù)資料
| 型號： | 935268252551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 77/80頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 935268252551 |
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Philips Semiconductors
Errata To the PDI1394L40 1394 AV Link Layer Controller (Data Sheet dated: 2000 December 15).
15 December 2000 – Page 76
ERRATA FOR THE PHILIPS
PDI1394L40 1394 ENHANCED AV LINK LAYER CONTROLLER
(This errata list refers only to version 0301 of the L40 chip... package date codes after 0030
and the L40 Data Sheet dated 2000 December 15)
Chip Errata:
E–1
AV1READY pin initialization state (after hardware reset of the chip)
Description of expected operation: This pin should be in an output state with a LOW level applied immediately after power on reset
and after any subsequent hardware reset.
Description of observed behavior: The AV1READY pin is in an undefined output state (with level being HIGH or
LOW) after power–up and after subsequent hardware resets of the L40.
Solution or work around: The host controller software power–up routine should be modified to place the pin
state in the proper condition (as it will be used later) immediately after power–up and after any subsequent hardware
reset. The proper state of the pin can be set by means of the GLOBCSR register (0x018), by placing the proper states on bits 16 and
17, DIRAV1 and ENOUTAV1.
E–2
Register 0x008, LNKPHYINTACK, bit 11 is set at all times.
Description of expected operation: This bit position is not used and therefore should indicate a ”0” or reset condition
at all times.
Description of observed behavior: This bit always indicates a ”1” state.
Solution or work around: Ignore the state of this bit in this register. The reset state of this register is ”00000800”
instead of the data sheet indicated ”00000000”. The state of this bit will be changed to ”0” in subsequent versions
of this part.
E–3
RDI register bits do not function properly when the L40 part is used with PDI1394P11A PHY.
Description of expected operation: When the L40 is placed in power–down mode (either by setting the SWPD bit in the RDI register
or placing the PD pin in the HIGH state), the L40 stops producing the LPS signal and the PHY interprets this lack of LPS signal as the
impetus to remove the SYSCLK (system clock) from the link – PHY interface. This action causes the L40 to enter power–down mode
and should place the SCA bit LOW, the PLI bit LOW, and the SCI bit HIGH.
Description of observed behavior: The SCA, PLI and SCI bits of the RDI register do not reset / set when SWPD or the PD pin is as-
serted. This is due to the fact that the SYSCLK output of the P11A PHY remains HIGH when the clock is stopped. The SCA and PLI
bits will erroneously read as if the L40 is powered up, they will both remain HIGH. The SCI bit, which is normally set (1) when the
L40 is powered–down, will remain reset (0) in this case. Reading the status of these bits in the RDI register will give a false indication
that the L40 is operating when it is not.
Solution or work around: A hardware work–around for this problem exists. It consists of adding a pull down resistor to set a low dc
bias level on the SCLK input of the L40 so as to make the pin go to the LOW state when the clock is not present. The value of the
resistor is R= 3.3 KOhms; a 1/10th watt type is sufficient.
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