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參數(shù)資料
| 型號(hào)： | 935268252551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁(yè)數(shù)： | 55/80頁(yè) |
| 文件大?。?/td> | 306K |
| 代理商： | 935268252551 |
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Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
56
13.2.9
Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044
This quadlet represents the last received header value when AV receiver is operating.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPH
QPC
FN
DBS
SV00286
E0
F0
31 30
SID
Reset Value 0x00000000
Bit 31..30:
R
E0: End of Header, F0: Format: Always set to 00 for first AV header quadlet.
Bit 29..24
R
SID: Source ID, contains the node address of the sender of the isochronous data.
Bit 23.16:
R
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
Bit 15..14:
R
FN (Fraction Number): The encoding for the number of data blocks into which each source packet has been divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8) by the transmitter of the packet.
Bit 13..11:
R
QPC: Number of dummy quadlets appended to each source packet before it was divided into data blocks of the
specified size.
Bit 10:
R
SPH: Indicates that a CYCTM based time stamp is inserted before each application packet (25 bits specified in the
IEC 61883 International Standard).
13.2.10
Common Isochronous Receiver Packet Header Quadlet 2 (IRXHQ2) – Base Address: 0x048
E1
F1
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT
SYT
SV00287
31 30
FDF
Reset Value 0x0000FFFF
Bit 31..30:
R
E1: End of Header, F1: Format: Should be set to 10 for second AV header quadlet.
Bit 29..24:
R
FMT: Value inserted in the Format field.
Bit 23..0:
R
FDF/SYT: If ‘‘EN FS” in Register IRXPKCTL (0x040) is set to ‘1’, then lower 16-bits are interpreted as SYT.
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