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參數(shù)資料
| 型號： | 935268252551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 44/80頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 935268252551 |
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Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
46
Bit 22:
R
Little Endian (LTLEND): Refers to the state of the endianess of the data and address lines connected to the ’L40.
This bit reflects the state of the AV2ERR0/LTLEND pin during power reset. The state of this pin is read during reset
and that state is latched into this bit position. When LTLEND = 0, the chip is set to receive BIG ENDIAN address and
data on its host interface (HIF). When LTLEND = 1, the Link chip will receive LITTLE ENDIAN oriented data
and address information. If this bit is set (1), the state of the DATAINV pin will also become important for
determination of data positions in the internal link registers. See the section on Big and Little Endian Modes for more
information (Section 12.5.3).
Bit 21:
R/W
Reset Transmitter (RSTTx): When set to one, this synchronously resets the transmitter within the link layer.
Bit 20:
R/W
Reset Receiver (RSTRx): When set to one, this synchronously resets the receiver within the link layer.
Bit 18:
R/W
Reset PHY-Link interface (RPL): Resets the PHY–Link interface in accordance with 1394a requirements.
Note: This bit automatically resets to “0” when the interface reset operation has been completed. The PHY–Link
reset operation occurs very quickly, reading this bit accurately is not usually possible.
Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in the
following state of operation:
1) The isochronous transmit FIFO is not receiving data for transmission
2) The isochronous transmitter is disabled
3) No asynchronous packets are being generated for transmission
4) Both the ASYNC request and response queues are empty
Bit 12:
R/W
Strict Isochronous (STRICTISOCH): Used to accept or reject isochronous packets sent outside of specified
isochronous cycles (between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified
cycles, a “0” accepts isochronous packets sent outside the specified cycle.
Bit 11:
R/W
Cycle Master (CYMASTER): When asserted and the PDI1394L40 is attached to the root PHY (ROOT bit = 1), and
the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master
function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle
Master function in such a case, first reset CYMASTER, then set it again.
Bit 10:
R/W
Cycle Source (CYSOURCE): When asserted, the cycle_count field increments and the cycle_offset field resets for each
positive transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field rolls over.
Bit 9:
R/W
Cycle Timer Enable (CYTIMREN): When asserted, the cycle offset field increments. When deasserted, the Cycle
Timer Register (0x010, CYCTM) can be used as a general read write register for Host Interface Firmware testing.
Bit 6:
R
Transmitter Ready (TxRDY): The transmitter is idle and ready.
Bit 5:
R
Root (ROOT): Indicates this device is the root on the bus. This automatically updates after the self_ID phase.
Bit 4:
R
Busy Flag (BUSYFLAG): The type of busy acknowledge which will be sent next time an acknowledge is required.
0 = Busy A, 1 = Busy B (only meaningful during a dual-phase busy/retry operation).
Bit 3..0:
R
AT acknowledge received (ATACK): The last acknowledge received by the transmitter in response to a packet sent
from the transmit-FIFO interface while the ATF is selected (diagnostic purposes).
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