參數(shù)資料
型號(hào)： 935268252551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁(yè)數(shù)： 52/80頁(yè)
文件大?。?/td> 306K
代理商： 935268252551
Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
53
13.2.4
Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C
The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter.
Bits 2, 3, and 4 “auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to
clear these interrupts to be alerted the next time.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCARD
ITXFULL
ITXEMPTY
DBCERR
INPERR
TRMBP
TRMSYT
PLDSCI
ITXMFI
ITXMEI
DBCEI
IDDSCI
EOTI
SYTTI
SV01842
31 30
IT512LFT
IT256LFT
IT100LFT
Reset Value 0x00000000
Bits 9 .. 0 are interrupt acknowledge bits; and are defined as:
Bit 9:
R/W
IT100LFT: Interrupt when transmitter queue reaches 100 quadlets from full.
Bit 8:
R/W
IT256LFT: Interrupt when transmitter queue reaches 256 quadlets from full.
Bit 7:
R/W
IT512LFT: Interrupt when transmitter queue reaches 512 quadlets from full. This bit is disabled if 0.5K Byte buffer
size is set.
Bit 6:
R/W
TRMSYT: Interrupt on transmission of a SYT in CIP header quadlet 2
Bit 5:
R/W
TRMBP: Interrupt on payload transmission/discard complete.
Bit 4:
R/W
DBCERR: Acknowledge interrupt on Data Block Count (DBC) synchronization loss.
Bit 3:
R/W
INPERR: Acknowledge interrupt on input error (input data discarded).
Bit 2:
R/W
DISCARD: Interrupt on lost cycle (payload discarded).
Bit 1:
R/W
ITXFULL: Interrupt on isochronous memory bank full. This is a fatal error. The ITX transmitter will reset itself
automatically when this occurs.
Bit 0:
R/W
ITXEMPTY: Interrupt on isochronous memory bank empty.
Other bits will always read ‘0’.
13.2.5
Isochronous Transmitter Interrupt Enable (ITXINTE) – Base Address: 0x030
These are the enabled bits for the AV Transmitter Control.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5 4
3
2 1
0
EDISCARD
EITXFULL
EITXEMPTY
EDBCERR
EINPERR
ETRMBP
ETRMSYT
PLDSCI
ITXMFI
ITXMEI
DBCEI
IDDSCI
EOTI
SYTTI
31 30
SV01843
EIT512LFT
EIT256LFT
EIT100LFT
Reset Value 0x00000000
Bits 13..0 are interrupt enable bits for the Isochronous Transmitter Interrupt Acknowledge register (ITXINTACK).
相關(guān)PDF資料
PDF描述
08008GOC 125 A, 800 V, SCR, TO-209AC
08008GOD 125 A, 800 V, SCR, TO-208AD
08010GOB 125 A, 1000 V, SCR, TO-209AC
08010GOC 125 A, 1000 V, SCR, TO-209AC
08010GOD 125 A, 1000 V, SCR, TO-208AD
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