參數(shù)資料
型號(hào)： 935268252551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁(yè)數(shù)： 54/80頁(yè)
文件大?。?/td> 306K
代理商： 935268252551
Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
55
13.2.8
Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040
NOTE: When receiver reset is required, first disable receiver (EN_IRX = 0), then wait until Rx FIFO is emptied, then perform the reset. This will
allow previously received packets to go to the application instead of being lost.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_FS
RST_IRX
EN_IRX
SP
A
V
RMVUAP
SV00887
BPAD
31 30
RXAP_CLK
DIS_TSC
SNDIMM
Reset Value 0x00000041
AV Receiver Control Bits.
Bit 29..28:
R/W
RXAP_CLK: Receiver Application Clock, default mode, ‘00’ the AVxCLK pin is an input. This pin can become an
application clock and output for the isochronous Receiver by programming it to ‘01’, ‘10’, or ‘11’.
The programming values are:
00
Input
01
24.576MHz
10
12.288MHz
11
6.144MHz
Note that when enabled as ‘01’, ‘10’, or ‘11’, the AV port that is configured as receiver and enabled will output this
clock signal on its AVxCLK pin.
Bit 8:
R/W
SNDIMM: Send immediately; when set to “1”, this bit will allow a received isochronous packet containing a CRC
error to be output immediately (without regard to the time stamp value). This bit defaults to “0”. In default (reset)
mode, the packet will be output with respect to the time stamp value, even if there is a CRC error.
CAUTION: If there is an error in the time stamp, the packet may be held far into the future. This will affect
subsequently received packets.
Bit 7:
R/W
DIS_TSC: Disable Time Stamp Checking. Defaults to “0”, time stamp checking is enabled. When time stamp
checking is disabled, the time stamp accompanying a packet is output before the packet to the application for use
by the application. This adds an extra quadlet of data to the received data stream; the application must be capable
of handling this extra 4 bytes.
Bit 6:
R/W
RMVUAP: Remove unreliable packets from memory, do not attempt delivery
Bit 5:
R
SPAV: Source packet available for delivery in buffer memory.
Bit 4:
R/W
EN_IRX: Enable receiver operation. Value is only checked whenever a new bus packet arrives, so enable/disable
while running is ‘graceful’, meaning any transfers in process will be completed before this bit is asserted.
Bit 2..3:
R/W
BPAD: Value indicating the amount of byte padding to be removed from the last data quadlet of each source packet,
from 0 to 3 bytes. This is in addition to quadlet padding as defined in IEC 61883 International Standard.
Bit 1:
R/W
EN_FS: Enable processing of SYT stamps.
Bit 0:
R/W
RST_IRX: causes the receiver to be reset when ‘1’. In order for synchronous reset of IRX to work properly, the
application must supply an AVCLK and ensure that the reset bit is kept (programmed) HIGH for at least the duration
of one AVCLK period. Failure to do so may cause the application interface of this module to be improperly reset (or
not reset at all).
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