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參數(shù)資料
| 型號(hào)： | 82595TX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 643K |
| 代理商： | 82595TX |
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82595FX
5.4 82595FX Status Interface
The Status of the 82595FX can be read from Regis-
ter 1 of Bank 0, with additional status information
contained in Register 0 (the Command Register).
Figure 5-3 shows these registers. Other information
concerning the configuration and initialization of the
82595FX and its registers can be obtained by direct-
ly reading the 82595FX registers.
When read, the Command OP Code field indicates
which event (MC Done, Init Done, TDR Done, or
DIAG Done) has been completed. This field is valid
only when the EXEC INT Bit (Bank 0, Reg 1, Bit 3) is
set to a 1. Reading the Pointer field indicates which
bank the 82595FX is currently operating in. Register
1 in Bank 0 contains the 82595FX interrupts status
as well as the current states of the RCV and Execu-
tion units of the 82595FX. Resultant status from
events such as the completion of a transmission or
the reception of an incoming frame is contained in
the status field of the memory structures for these
particular events.
6.0
INITIALIZATION
Upon either a software or hardware RESET, the
82595FX enters into its initialization sequence.
When the 82595FX is interfaced to an ISA bus, the
82595FX reads information from its EEPROM and
Jumper block (if utilized) which configures critical pa-
rameters (IO Address mapping, etc.) to allow initial
accesses to the 82595FX during the host system’s
initialization sequence and also access by the soft-
ware device driver. The 82595FX can also be config-
ured (via the EEPROM) to automatically resolve any
conflicts to its IO address location either by moving
its IO address offset to an unused location in the
case that a conflict occurs, or by using the Plug N’
Play Software to the I/O address location. This pro-
cess eliminates a large majority of LAN end-user
setup problems.
The 82595FX can be configured to operate with ISA
systems that require early deassertion of the
IOCHRDY signal to its low (not ready) state. The
82595FX, along with its software driver, can perform
a test at initialization to determine if early IOCHRDY
deassertion is required.
7
6
5
4
3
2
1
0
Pointer
ABORT
EXECUTION EVENT
Reg 0 (CMD Reg)
RCV
States
EXEC
States
EXEC
INT
TX
INT
RX
INT
RX STP
INT
Reg 1 (Bank 0)
Figure 5-3. 82595FX Status Information
22
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| 82596DX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
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