參數(shù)資料
型號(hào)： 82595TX
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 13/54頁(yè)
文件大?。?/td> 643K
代理商： 82595TX
82595FX
3.0
82595FX INTERNAL
ARCHITECTURE OVERVIEW
Figure 1 shows a high level block diagram of the
82595FX. The 82595FX is divided into four main
subsections; a system interface, a local memory
sub-system interface, a CSMA/CD unit, and a serial
interface.
3.1 System Interface Overview
The 82595FX’s system interface subsection in-
cludes a glueless ISA bus interface, and the
82595FX’s IO registers (including the 82595FX’s
command, status, and Data In/Out registers). The
system interface block also interfaces with the
82595FX’s local memory interface subsystem and
CSMA/CD subsystem.
The bus interface logic provides the control, ad-
dress, and data interface to an ISA compatible bus.
The 82595FX decodes up to 1M of total memory
address space. Address decoding within 16K block
increments (A14–A19) are used for Flash or Boot
EPROM. IO accesses are decoded throughout the 1
Kbyte PC IO address range (A10 and A11 provide up
to 4K of IO addressing and are used for Plug N’
Play). The 82595FX data bus interface provides ei-
ther an 8- or 16-bit interface to the host system’s
data bus. The control interface provides complete
handshaking interface with the system bus to enable
transfer of data between the 82595FX solution and
the host system.
The 82595FX’s IO registers provide 3 banks of di-
rectly addressable registers which are used as the
control and data interface to the 82595FX. There
are 16 IO registers per bank, with only one bank
enabled at a time. This allows the complete
82595FX software interface to be contained in one
16-byte IO space. The base address of this IO space
is selectable via either software (which can be
stored in a serial EEPROM), or by strapping the
82595FX IO Jumper block (J0–J2). The 82595FX
can also detect conflicts to its base IO space, and
automatically resolve these conflicts either by allow-
ing the selection of one Plug N’ Play card from multi-
ple cards (using Plug N’ Play software), or by map-
ping itself into an un-used IO space (Automatic IO
Resolution). Included in the 82595FX IO registers
are the Command Register, the Status Register, and
the Local Memory IO Port register, which provides
the data interface to the local SRAM buffer con-
tained in an 82595FX solution. Functions such as IO
window mapping, Interrupt enable, RCV and XMT
buffer initialization, etc. are also configured and con-
trolled through the IO registers.
3.1.1 CONCURRENT PROCESSING
FUNCTIONALITY
The 82595FX’s Concurrent Processing feature sig-
nificantly enchances data throughput performance
by performing both system bus and serial link activi-
ties concurrently. Transmission of a frame is started
by the 82595FX before that frame is completely cop-
ied into local memory. During reception, a frame is
processed by the host CPU before that frame is en-
tirely copied to local memory. Transmit Concurrent
Processing feature is enabled by writing to BANK 2,
Register 1, Bit 0. A 1 written to this bit enables this
functionality, a 0 (default) disables it. To enable Re-
ceive Concurrent Processing, BANK 1, Register 7
must be programmed to value other than 00h (00h
disables RCV Concurrent Processing, and is de-
fault). (See Section 4.1 for the format of IO BANK 1
and 2.) Improvements in concurrent processing
functionality have allowed the 82595FX to include
enhancements to the throughput efficiency of the
82595TX. For details, refer to the 82595FX User’s
Guide. Concurrent Processing is not recommended
for 8-bit interfaces. For more information on Trans-
mit and Receive Concurrent Processing, refer to
Section 7.0 and Section 8.0.
3.2 Local Memory Interface
The 82595FX’s local memory interface includes a
DMA unit which controls data transfers to or from
the 82595FX’s local SRAM, control for access to a
Boot EPROM/FLASH, and two interfaces to a serial
EEPROM. The local memory interface subsection
also arbitrates accesses to the local memory by the
host CPU and the 82595FX.
Data transfers between the 82595FX and the local
SRAM are always through the 82595FX’s Local
Memory 16-bit/32-bit IO Port. This allows the entire
SRAM memory (up to 64 Kbytes) to be mapped into
one IO location in the host systems IO map. By
setting a configuration bit in the 82595FX’s IO
Registers (32IO/HAR
Y
), the local memory can be
extended from 16 bits to a full 32 bits. During 32-bit
accesses, the CPU would perform a doubleword ac-
cess addressed to register 12 of BANK0. The ISA
bus will break this access up into two 16-bit access-
es to Registers 12/13 followed by Registers 14/15,
(or 4 sequential 8-bit accesses in an 8-bit interface).
The CPU always accesses the 82595FX IO Port for
Receive or Transmit data transfers, while the
82595FX automatically increments the address to
the SRAM after each CPU access. The SRAMs data
path is an 8-bit interface (typically 64K by 8-bits
wide, or 256K by 8-bits wide) to allow for the lowest
possible solution cost. The 82595FX implements a
13
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