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88
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Signal Definitions
BINIT#
I/O
BINIT# (Bus Initialization) may be observed and driven by all processor front
side bus agents. If used, BINIT# must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled, BINIT# is asserted to signal any bus
condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration (see
Section 8.1
) and BINIT# is sampled asserted, symmetric agents reset their bus
LOCK# activity and bus request arbitration state machines. The bus agents
do not
reset their I/O Queue (IOQ) and transaction tracking state machines
upon observation of BINIT# assertion. Once the BINIT# assertion has been
observed, the bus agents will re-arbitrate for the front side bus and attempt
completion of their bus queue and IOQ entries.
If BINIT# observation is enabled during power on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling
architecture of the system.
BNR#
I/O
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who
is unable to accept new bus transactions. During a bus stall, the current bus
owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR#
is a wire-OR signal which must connect the appropriate pins of all processor
system bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, BNR# is activated on
specific clock edges and sampled on specific clock edges.
BOOT_
SELECT
I
The BOOT_SELECT input informs the processor whether the platform
supports the processor. Incompatible platform designs will have this input
connected to V
. Thus, this pin is essentially an electrical key to prevent the
processor from running in a system that is not designed for it. For platforms that
are designed to support the 64-bit Intel
Xeon processor MP with up to 8MB
L3 cache, this pin should be a no-connect.
BPM[5:0]#
I/O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins of all processor
front side bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY#
is a processor output used by debug tools to determine processor debug
readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port.
PREQ# is a processor input and is used by debug tools to request debug
operation of the processors.
BPM[5:4]# must be bussed to all bus agents.
BPRI#
I
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor front side bus. It must connect the appropriate pins of all processor
front side bus agents. Observing BPRI# active (as asserted by the priority
agent) causes all other agents to stop issuing new requests, unless such
requests are part of an ongoing locked operation. The priority agent keeps
BPRI# asserted until its requests are issued, then releases the bus by
deasserting BPRI#.
Table 6-1. Signal Definitions (Sheet 2 of 9)
Name
Type
Description