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參數(shù)資料
| 型號(hào)： | 80546KF |
| 廠商： | Intel Corp. |
| 英文描述： | 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache |
| 中文描述： | 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存 |
| 文件頁數(shù)： | 38/138頁 |
| 文件大?。?/td> | 2666K |
| 代理商： | 80546KF |
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38
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a
166 MHz BCLK[1:0].
2. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2). Min period specification is based on -300 PPM deviation from a 6 ns
period. Max period specification is based on the summation of +300 PPM deviation from a 6 ns period and a
+0.5% maximum variance due to spread spectrum clocking.
3. For the clock jitter specification, refer to the applicable clock driver design specification.
4. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
5. Rise and fall times are measured single-ended between 245 mV and 455 mV of the clock swing.
.
NOTES:
1. These parameters are based on design characterization and are not tested.
2. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V
) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
3. Valid delay timings for these signals are specified into the test circuit described in
Figure 2-6
and with
GTLREF at 0.63
*
V
± 2%.
4. Specification is for a minimum swing defined between V
IL_MAX
to V
IH_MIN
. This assumes an edge rate of
0.9 V/ns to 1.2 V/ns.
5. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
6. This should be measured after V
and BCLK[1:0] become stable.
7. Maximum specification applies only while PWRGOOD is asserted.
.
Table 2-20. Front Side Bus Differential Clock Specifications
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
1
FSB Clock Frequency
165.78
166.72
MHz
T1: BCLK[1:0] Period
5.9982
6.0320
ns
2-8
2
T2: BCLK[1:0] Period Stability
175
ps
3,4
T3: BCLK[1:0] Rise Time
175
700
ps
5
T4: BCLK[1:0] Fall Time
175
700
ps
5
Table 2-21. Front Side Bus Common Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2
T10: Common Clock Output Valid Delay
-0.125
1.470
ns
2-10
3
T11: Common Clock Input Setup Time
0.810
N/A
ns
2-10
4
T12: Common Clock Input Hold Time
0.355
N/A
ns
2-10
4
T13: RESET# Pulse Width
1.00
10.00
ms
2-18
5,6,7
Table 2-22. Front Side Bus Source Synchronous AC Specifications (Sheet 1 of 2)
T# Parameter
Min
Typ
Max
Unit
Figure
Notes
1,2,3
T20: Source Sync. Output Valid Delay
(first data/address only)
-0.150
1.400
ns
2-11,2-12
4
T21: T
Source Sync. Data Output
Valid Before Data Strobe
0.400
ns
2-12
4,7
T22: T
Source Sync. Data Output
Valid After Data Strobe
0.400
ns
2-12
4,8
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