
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
35
Electrical Specifications
NOTES:
1. V
IL
is defined as the voltage level at a receiving agent that will be interpreted as a logical low value.
2. V
IH
is defined as the voltage level at a receiving agent that will be interpreted as a logical high value.
3. V
and V
may experience excursions above V
CC
. However, input signal drivers must comply with the signal
quality specifications in
Section 3
.
4. Refer to Processor Signal Integrity Models for I/V characteristics.
5. The V
referred to in these specifications refers to the instantaneous V
TT
.
6. Leakage to V
with pin held at V
.
7. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
8. Leakage to V
TT
with pin held at 300 mV.
NOTES:
1. All outputs are open drain.
2. TAP signal group must meet system signal quality specification in
Section 3
.
3. Refer to the Processor Signal Integrity Models for I/V characteristics.
4. The V
referred to in these specifications refers to instantaneous V
.
5. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
6. V
HYS
represents the amount of hysteresis, nominally centered about 0.5 * V
TT
for all TAP inputs.
Table 2-15. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
V
IL
Input Low Voltage
0.0
GTLREF - (0.10 * V
TT
)
V
1,5
V
IH
Input High Voltage
GTLREF + (0.10 * V
TT
)
V
TT
V
2,3,5
V
OH
Output High Voltage
0.90 * V
TT
V
TT
V
3,5
I
OL
Output Low Current
N/A
V
/
(0.50 * Rtt_min + R
ON
_min
|| R
L
)
±
200
±
200
mA
7
I
LI
Input Leakage Current
N/A
μA
6
I
LO
Output Leakage Current
N/A
μA
8
R
ON
Buffer On Resistance
8
12
W
4
Table 2-16. PWRGOOD and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1
V
HYS
Input Hysteresis
200
350
mV
6
V
T+
Input Low to High
Threshold Voltage
0.5 * (V
TT
+ V
HYS_MIN
)
0.5 * (V
TT
+ V
HYS_MAX
)
V
4
V
T-
Input High to Low
Threshold Voltage
0.5 * (V
TT
- V
HYS_MAX
)
0.5 * (V
TT
- V
HYS_MIN
)
V
4
V
OH
Output High Voltage
N/A
V
TT
V
2,4
I
OL
Output Low Current
45
mA
5
I
LI
Input Leakage Current
±200
μA
I
LO
Output Leakage Current
±200
μA
R
ON
Buffer On Resistance
8
12
3