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參數(shù)資料
| 型號： | 80546KF |
| 廠商： | Intel Corp. |
| 英文描述： | 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache |
| 中文描述： | 64位Intel Xeon處理器MP的高達(dá)8MB三級高速緩存 |
| 文件頁數(shù)： | 27/138頁 |
| 文件大?。?/td> | 2666K |
| 代理商： | 80546KF |
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64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
27
Electrical Specifications
2.7
GTL+ Asynchronous and AGTL+ Asynchronous
Signals
The processor does not utilize CMOS voltage levels on any signals that connect to the processor
silicon. As a result, inputs signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, SMI#, and STPCLK# utilize GTL buffers. Legacy output THERMTRIP# utilizes a
GTL+ output buffer. All of these asynchronous signals follow the same DC requirements as GTL+
signals; however, the outputs are not driven high (during the logical 0-to-1 transition) by the
processor. FERR#/PBE#, IERR#, and PROCHOT# have now been defined as AGTL+
asynchronous signals as they include an active pMOS device. GTL+ asynchronous and AGTL+
asynchronous signals do not have setup or hold time specifications in relation to BCLK[1:0].
However, all of the GTL+ asynchronous and AGTL+ asynchronous signals are required to be
asserted/deasserted for at least six BCLKs in order for the processor to recognize the proper signal
state, except during power-on configuration (see
Table 2-24
for the proper specifications at
RESET). See
Table 2-17
and
Table 2-23
for the DC and AC specifications for the GTL+
asynchronous and AGTL+ asynchronous signal groups.
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the TAP logic, Intel recommends that
the processor(s) be first in the TAP chain, followed by any other components within the system.
Use of a translation buffer to connect to the rest of the chain is recommended unless one of the
other components is capable of accepting an input of the appropriate voltage. Similar
considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each signal
may be required, each driving a different voltage level.
2.9
Maximum Ratings
Table 2-8
specifies absolute maximum and minimum ratings. Within functional operation limits,
functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute maximum and
minimum ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to conditions
outside these limits, but within the absolute maximum and minimum ratings, the device may be
functional, but with its lifetime degraded depending on exposure to conditions exceeding the
functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-
term reliability can be expected. Moreover, if a device is subjected to these conditions for any
length of time then, when returned to conditions within the functional operating condition limits, it
will either not function, or its reliability will be severely degraded.
Although the processor contains protective circuitry to resist damage from static electric discharge,
precautions should always be taken to avoid high static voltages or electric fields.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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