參數(shù)資料
型號(hào)： 80546KF
廠商： Intel Corp.
英文描述： 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache
中文描述： 64位Intel Xeon處理器MP的高達(dá)8MB三級(jí)高速緩存
文件頁(yè)數(shù)： 40/138頁(yè)
文件大?。?/td> 2666K
代理商： 80546KF
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40
64-bit Intel
Xeon Processor MP with up to 8MB L3 Cache Datasheet
Electrical Specifications
NOTES:
1. All AC timings for the GTL+ asynchronous signals are referenced to the BCLK0 rising edge at Crossing
Voltage (V
). All GTL+ asynchronous signal timings are referenced at GTLREF. PWRGOOD is
referenced to the BCLK0 rising edge at 0.5 * V
TT
.
2. These signals may be driven asynchronously.
3. Refer to the PWRGOOD definition for more details regarding the behavior of the signal.
4. Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion
or deassertion of PROCHOT# for the processor to enable or disable the TCC. Additionally, time is allocated
after the assertion or deassertion of PROCHOT# for the processor to complete current instruction execution.
This specification applies to the PROCHOT# signal when asserted by the processor and the FORCEPR#
signal when asserted by the system.
5. Refer to
Section 8.2
for additional timing requirements for entering and leaving low power states.
6. Intel recommends the V
power supply also be removed upon assertion of THERMTRIP#.
7. A minimum pulse width of 500us is recommended when FORCEPR# is asserted by the system.
NOTES:
1. Before the clock that de-asserts RESET#
2. After the clock that de-asserts RESET#.
NOTES:
1. Not 100% tested. These parameters are based on design characterization.
2. This specification is based on the capabilities of the ITP-XDP debug port tool, not on processor silicon.
3. Referenced to the rising edge of TCK.
4. Referenced to the falling edge of TCK.
5. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
T38: PROCHOT#, FORCEPR# pulse width
500
μs
2-14
4
T39: THERMTRIP# assertion until V
CC
and
V
CACHE
removal
500
ms
2-15
6
T40: FERR# valid delay from STPCLK#
deassertion
0
5
BCLKs
2-20
T41: V
CC
to PWRGOOD assertion time
1
500
ms
2-18
Table 2-23. Miscellaneous Signals AC Specifications (Sheet 2 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,5
Table 2-24. Front Side Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T47: Reset Configuration Signals (A[21:16]#)
Setup Time
1
ms
1
T45: Reset Configuration Signals (A[39:22]#,
A[15:3]#, BR[3:0]#, INIT#, SMI#) Setup Time
4
BCLKs
2-18
1
T46: Reset Configuration Signals (A[39:3]#,
BR[3:0]#, INIT#, SMI#) Hold Time
2
28
BCLKs
2-18
2
Table 2-25. TAP Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,7
T55: TCK Period
13.3
ns
2-7
2
T61: TDI, TMS Setup Time
1.5
ns
2-13
3,6
T62: TDI, TMS Hold Time
3.0
ns
2-13
3,6
T63: TDO Clock to Output Delay
0.5
10.0
ns
2-13
4
T64: TRST# Assert Time
2
TCK
2-14
5
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