參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁(yè)數(shù)： 8/95頁(yè)
文件大小： 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
General Registers:
The eight 32-bit general pur-
pose registers are used to contain arithmetic and
logical operands. Four of these (EAX, EBX, ECX and
EDX) can be used either in their entirety as 32-bit
registers, as 16-bit registers, or split into pairs of
separate 8-bit registers.
Segment Registers:
Six 16-bit special purpose reg-
isters select, at any given time, the segments of
memory that are immediately addressable for code,
stack, and data.
Flags and Instruction Pointer Registers:
These
two 32-bit special purpose registers in Figure 2.1
record or control certain aspects of the 80376 proc-
essor state. The EFLAGS register includes status
and control bits that are used to reflect the outcome
of many instructions and modify the semantics of
some instructions. The Instruction Pointer, called
EIP, is 32 bits wide. The Instruction Pointer controls
instruction fetching and the processor automatically
increments it after executing an instruction.
Control Register:
The 32-bit control register, CR0,
is used to control Coprocessor Emulation.
System Address Registers:
These four special
registers reference the tables or segments support-
ed by the 80376/80386 protection model. These ta-
bles or segments are:
GDTR (Global Descriptor Table Register),
IDTR (Interrupt Descriptor Table Register),
LDTR (Local Descriptor Table Register),
TR (Task State Segment Register).
Debug Registers:
The six programmer accessible
debug registers provide on-chip support for debug-
ging. The use of the debug registers is described in
Section 2.11
Debugging Support
.
EFLAGS REGISTER
The flag Register is a 32-bit register named
EFLAGS. The defined bits and bit fields within
EFLAGS, shown in Figure 2.2, control certain opera-
tions and indicate the status of the 80376 processor.
The function of the flag bits is given in Table 2.1.
240182–3
240182–4
240182–5
Figure 2.2. Status and Control Register Bit Functions
8
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