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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 50/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
Sampling begins in T2 during Cycle 1 in Figure 4.10.
Once NA is sampled active during the current cycle,
the 80376 is free to drive a new address and bus
cycle definition on the bus as early as the next bus
state. In Figure 4.10, Cycle 1 for example, the next
address and status is driven during state T2P. Thus
Cycle 1 makes the transition to pipelined timing,
since it begins with T1 but ends with T2P. Because
the address for Cycle 2 is available before Cycle 2
begins, Cycle 2 is called a pipelined bus cycle, and it
begins with T1P. Cycle 2 begins as soon as READY
asserted terminates Cycle 1.
Examples of transition bus cycles are Figure 4.10,
Cycle 1 and Figure 4.9, Cycle 2. Figure 4.10 shows
transition during the very first cycle after an idle bus
state, which is the fastest possible transition into ad-
dress pipelining. Figure 4.9, Cycle 2 shows a tran-
sition cycle occurring during a burst of bus cycles. In
any case, a transition cycle is the same whenever it
occurs: it consists at least of T1, T2 (NA is asserted
at that time), and T2P (provided the 80376 has an
internal bus request already pending, which it almost
always has). T2P states are repeated if wait states
are added to the cycle.
Note that only three states (T1, T2 and T2P) are
required in a bus cycle performing a
transition
from
non-pipelined into pipelined timing, for example Fig-
ure 4.10, Cycle 1. Figure 4.10, Cycles 2, 3 and 4
show that pipelining can be maintained with two-
state bus cycles consisting only of T1P and T2P.
Once a pipelined bus cycle is in progress, pipelined
timing is maintained for the next cycle by asserting
NA and detecting that the 80376 enters T2P during
the current bus cycle. The current bus cycle must
end in state T2P for pipelining to be maintained in
the next cycle. T2P is identified by the assertion of
ADS. Figures 4.9 and 4.10 however, each show
pipelining ending after Cycle 4 because Cycle 4
ends in T2I. This indicates the 80376 didn’t have an
internal bus request prior to the acknowledgement
of Cycle 4. If a cycle ends with a T2 or T2I, the next
cycle will not be pipelined.
Realistically, pipelining is almost always maintained
as long as NA is sampled asserted. This is so be-
cause in the absence of any other request, a code
prefetch request is always internally pending until
the instruction decoder and code prefetch queue are
completely full. Therefore pipelining is maintained
for long bursts of bus cycles, if the bus is available
(i.e., HOLD inactive) and NA is sampled active in
each of the bus cycles.
INTERRUPT ACKNOWLEDGE (INTA) CYCLES
In repsonse to an interrupt request on the INTR in-
put when interrupts are enabled, the 80376 performs
two interrupt acknowledge cycles. These bus cycles
are similar to read cycles in that bus definition sig-
nals define the type of bus activity taking place, and
each cycle continues until acknowledged by READY
sampled active.
The state of A
2
distinguishes the first and second
interrupt acknowledge cycles. The byte address
driven during the first interrupt acknowledge cycle is
4 (A
23
–A
3
, A
1
, BLE LOW, A
2
and BHE HIGH). The
byte address driven during the second interrupt ac-
knowledge cycle is 0 (A
23
–A
1
, BLE LOW and BHE
HIGH).
The LOCK output is asserted from the beginning of
the first interrupt acknowledge cycle until the end of
the second interrupt acknowledge cycle. Four idle
bus states, T
i
, are inserted by the 80376 between
the two interrupt acknowledge cycles for compatibil-
ity with the interrupt specification T
RHRL
of the
8259A Interrupt Controller and the 82370 Integrated
Peripheral.
50
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