參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁數(shù)： 5/95頁
文件大?。?/td> 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
The following table lists a brief description of each pin on the 80376. The following definitions are used in
these descriptions:
The named signal is active LOW.
Input signal.
Output signal.
Input and Output signal.
No electrical connection.
I
O
I/O
D
Symbol
Type
Name and Function
CLK2
I
CLK2
provides the fundamental timing for the 80376. For additional
information see
Clock
in Section 4.1.
RESET
I
RESET
suspends any operation in progress and places the 80376 in a
known reset state. See
Interrupt Signals
in Section 4.1 for additional
information.
D
15
–D
0
I/O
DATA BUS
inputs data during memory, I/O and interrupt acknowledge
read cycles and outputs data during memory and I/O write cycles. See
Data Bus
in Section 4.1 for additional information.
A
23
–A
1
O
ADDRESS BUS
outputs physical memory or port I/O addresses. See
Address Bus
in Section 4.1 for additional information.
W/R
O
WRITE/READ
is a bus cycle definition pin that distinguishes write
cycles from read cycles. See
Bus Cycle Definition Signals
in Section
4.1 for additional information.
D/C
O
DATA/CONTROL
is a bus cycle definition pin that distinguishes data
cycles, either memory or I/O, from control cycles which are: interrupt
acknowledge, halt, and instruction fetching. See
Bus Cycle Definition
Signals
in Section 4.1 for additional information.
M/IO
O
MEMORY I/O
is a bus cycle definition pin that distinguishes memory
cycles from input/output cycles. See
Bus Cycle Definition Signals
in
Section 4.1 for additional information.
LOCK
O
BUS LOCK
is a bus cycle definition pin that indicates that other
system bus masters are denied access to the system bus while it is
active. See
Bus Cycle Definition Signals
in Section 4.1 for additional
information.
ADS
O
ADDRESS STATUS
indicates that a valid bus cycle definition and
address (W/R, D/C, M/IO, BHE, BLE and A
23
–A
1
) are being driven at
the 80376 pins. See
Bus Control Signals
in Section 4.1 for additional
information.
NA
I
NEXT ADDRESS
is used to request address pipelining. See
Bus
Control Signals
in Section 4.1 for additional information.
READY
I
BUS READY
terminates the bus cycle. See
Bus Control Signals
in
Section 4.1 for additional information.
BHE, BLE
O
BYTE ENABLES
indicate which data bytes of the data bus take part in
a bus cycle. See
Address Bus
in Section 4.1 for additional
information.
HOLD
I
BUS HOLD REQUEST
input allows another bus master to request
control of the local bus. See
Bus Arbitration Signals
in Section 4.1
for additional information.
5
相關(guān)PDF資料
PDF描述
804-2 RECTIFIERS ASSEMBLIES
804-3 RECTIFIERS ASSEMBLIES
804-4 RECTIFIERS ASSEMBLIES
8040AHL HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
8048AH HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
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