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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 26/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
Table 3.1. Access Rights Byte Definition for Code and Data Descriptors
Bit
Name
Function
Position
7
Present (P)
P
e
1
P
e
0
Segment is mapped into physical memory.
No mapping to physical memory exits
Segment privilege attribute used in privilege tests.
6–5
Descriptor Privilege
Level (DPL)
Segment
Descriptor (S)
4
S
e
1
S
e
0
Code or Data (includes stacks) segment descriptor
System Segment Descriptor or Gate Descriptor
3
2
Executable (E)
Expansion
Direction (ED)
Writable (W)
E
e
0
ED
e
0 Expand up segment, offsets must be
s
limit.
ED
e
1 Expand down segment, offsets must be
l
limit.
W
e
0 Data segment may not be written into.
W
e
1 Data segment may be written into.
Descriptor type is data segment:
If
Data
Segment
(S
e
1,
E
e
0)
1
*
3
2
Executable (E)
Conforming (C)
If
Code
Segment
(S
e
1,
E
e
1)
E
e
1
C
e
1
Descriptor type is code segment:
Code segment may only be executed when
CPL
t
DPL and CPL remains unchanged.
Code segment may not be read.
Code segment may be read.
1
Readable (R)
R
e
0
R
e
1
*
0
Accessed (A)
A
e
0
A
e
1
Segment has not been accessed.
Segment selector has been loaded into segment register
or used by selector test instructions.
generated that is a truncated version of this linear
address. Truncation will be to the maximum number
of address bits. It is recommended to place EPROM
at the highest physical address and DRAM at the
lowest physical addresses.
Code and Data Descriptors (S
e
1)
Figure 3.4 shows the general format of a code and
data descriptor and Table 3.1 illustrates how the bits
in the Access Right Byte are interpreted.
Code and data segments have several descriptor
fields in common. The accessed bit, A, is set when-
ever the processor accesses a descriptor. The gran-
ularity bit, G, specifies if a segment length is 1-byte-
granular or 4-Kbyte-granular. Base address bits
31–24, which are normally found in 80386 descrip-
tors, are not made externally available on the 80376.
They do not affect the operation of the 80376. The
A
31
–A
24
field should be set to allow an 80386 to
correctly execute with EPROM at the upper 4096
Mbytes of physical memory.
System Descriptor Formats (S
e
0)
System segments describe information about oper-
ating system tables, tasks, and gates. Figure 3.5
shows the general format of system segment de-
scriptors, and the various types of system segments.
80376 system descriptors (which are the same as
80386 descriptor types 2, 5, 9, B, C, E and F) contain
a 32-bit logical base address and a 20-bit segment
limit.
Selector Fields
A selector has three fields: Local or Global Descrip-
tor Table Indicator (TI), Descriptor Entry Index (In-
dex), and Requestor ( the selector’s) Privilege Level
(RPL) as shown in Figure 3.6. The TI bit selects ei-
ther the Global Descriptor Table or the Local De-
scriptor Table. The Index selects one of 8K descrip-
tors in the appropriate descriptor table. The RPL bits
allow high speed testing of the selector’s privilege
attributes.
Segment Descriptor Cache
In addition to the selector value, every segment reg-
ister has a segment descriptor cache register asso-
ciated with it. Whenever a segment register’s con-
tents are changed, the 8-byte descriptor associated
with that selector is automatically loaded (cached)
on the chip. Once loaded, all references to that seg-
ment use the cached descriptor information instead
of reaccessing the descriptor. The contents of the
descriptor cache are not visible to the programmer.
Since descriptor caches only change when a seg-
ment register is changed, programs which modify
the descriptor tables must reload the appropriate
segment registers after changing a descriptor’s
value.
26
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