參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁(yè)數(shù)： 34/95頁(yè)
文件大小： 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
phases, ‘‘phase one’’ and ‘‘phase two’’. Each CLK2
period is a phase of the internal clock. Figure 4.2
illustrates the relationship. If desired, the phase of
the internal processor clock can be synchronized to
a known phase by ensuring the falling edge of the
RESET signal meets the applicable setup and hold
times t
25
and t
26
.
DATA BUS (D
15
–D
0
)
These three-state bidirectional signals provide the
general purpose data path between the 80376 and
other devices. The data bus outputs are active HIGH
and will float during bus hold acknowledge. Data bus
reads require that read-data setup and hold times
t
21
and t
22
be met relative to CLK2 for correct oper-
ation.
ADDRESS BUS (BHE, BLE, A
23
–A
1
)
These three-state outputs provide physical memory
addresses or I/O port addresses. A
23
–A
16
are LOW
during I/O transfers except for I/O transfers auto-
matically generated by coprocessor instructions.
During coprocessor I/O transfers, A
22
–A
16
are driv-
en LOW, and A
23
is driven HIGH so that this ad-
dress line can be used by external logic to generate
the coprocessor select signal. Thus, the I/O address
driven by the 80376 for coprocessor commands is
8000F8H, and the I/O address driven by the 80376
processor for coprocessor data is 8000FCH or
8000FEH.
The address bus is capable of addressing 16 Mbytes
of
physical
memory
space
0FFFFFFH), and 64 Kbytes of I/O address space
(000000H through 00FFFFH) for programmed I/O.
The address bus is active HIGH and will float during
bus hold acknowledge.
(000000H
through
The Byte Enable outputs BHE and BLE directly indi-
cate which bytes of the 16-bit data bus are involved
with the current transfer. BHE applies to D
15
–D
8
and BLE applies to D
7
–D
0
. If both BHE and BLE are
asserted, then 16 bits of data are being transferred.
See Table 4.1 for a complete decoding of these sig-
nals. The byte enables are active LOW and will float
during bus hold acknowledge.
Table 4.1. Byte Enable Definitions
BHE
BLE
Function
0
0
Word Transfer
0
1
Byte Transfer on Upper Byte of the Data Bus, D
15
–D
8
1
0
Byte Transfer on Lower Byte of the Data Bus, D
7
–D
0
1
1
Never Occurs
34
相關(guān)PDF資料
PDF描述
804-2 RECTIFIERS ASSEMBLIES
804-3 RECTIFIERS ASSEMBLIES
804-4 RECTIFIERS ASSEMBLIES
8040AHL HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
8048AH HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
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