參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁數(shù)： 51/95頁
文件大小： 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
240182–28
Interrupt Vector (0–255) is read on D0–D7 at end of second Interrupt Acknowledge bus cycle.
Because each Interrupt Acknowledge bus cycle is followed by idle bus states, asserting NA has no practical effect.
Choose the approach which is simplest for your system hardware design.
Figure 4.13. Interrupt Acknowledge Cycles
During both interrupt acknowledge cycles, D
15
–D
0
float. No data is read at the end of the first interrupt
acknowledge cycle. At the end of the second inter-
rupt acknowledge cycle, the 80376 will read an ex-
ternal interrupt vector from D
7
–D
0
of the data bus.
The vector indicates the specific interrupt number
(from 0–255) requiring service.
HALT INDICATION CYCLE
The 80376 execution unit halts as a result of execut-
ing a HLT instruction. Signaling its entrance into the
halt state, a halt indication cycle is performed. The
halt indication cycle is identified by the state of the
bus definition signals and a byte address of 2. See
the
Bus Cycle Definition Signals
section. The halt
indication cycle must be acknowledged by READY
asserted. A halted 80376 resumes execution when
INTR (if interrupts are enabled), NMI or RESET is
asserted.
51
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