- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄293971 > 5962R0150202VYX 16-BIT, 16 MHz, RISC PROCESSOR, QFP132 PDF資料下載
參數(shù)資料
| 型號： | 5962R0150202VYX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16 MHz, RISC PROCESSOR, QFP132 |
| 封裝： | FP-132 |
| 文件頁數(shù)： | 8/53頁 |
| 文件大?。?/td> | 458K |
| 代理商： | 5962R0150202VYX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
16
UART Receiver Register (RCVR)
The UART Receiver Buffer Register (see figure 9) receives
9600-baud asynchronous serial data through the UARTIN input
pin on the UT1750AR. Each serial data string contains an active-
low Start bit, eight Data bits, an odd Parity bit, and an active-
high Stop bit. Figure 10 shows a single serial data string.
While receiving a serial data string, the UT1750AR generates
four status flags: Data Ready (DR); Overrun Error (OE);
Framing Error (FE); and Parity Error (PE). The UT1750AR
stores these status bits in the System Status Register (STATUS).
Receiver buffer register bits 15-8 are always low. Bit numbers
7-0 (RCD7-RCD0) contain data the UT1750AR receives via the
serial data port. RCD7 is the MSB; RCD0 is the LSB.
UART Transmitter Buffer Register (TXMT)
The UT1750AR’s internal UART forms an 11-bit serial data
string by combining a Start bit, the eight Data bits from the
Transmitter Buffer Register (TXMT), an odd Parity bit, and a
Stop bit. Figure 11 shows the composition of the serial data
string.
The UT1750AR transmits this serial data string through the
UARTOUT pin at a rate of 9600 baud.
Two status signals are associated with transmitting serial data.
These signals are the UART Transmitter Buffer Empty (TBE)
and UART Transmitter Register Empty (TE). TBE and TE are
both active high and provide information on the status of double
buffering the UART’s transmitted data. TBE and TE are read
from the System Status Register as bits 2 and 1, respectively.
The UT1750AR’s internal UART has a double-buffered data
transmission scheme (figure 12). The UT1750AR first loads the
data for transmission into the Transmitter Buffer Register. If the
UART Transmitter Register is empty, data from the TXMT
automatically transfers to the UART Transmitter Register. At
this time, the TBE bit goes active indicating more data may be
loaded into the TXMT. This double-buffering scheme allows
contiguous transmission of serial data streams and also
decreases the UT1750AR’s required overhead for the UART
interface.
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
0
5
0
4
0
3
0
2
0
1
0
7
0
6
0
6
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
MSB
LSB
Figure 9. The UART Receiver
5
4
T
3
R
2
0
1
S
T
D
7
R
C
D
R
C
D
R
C
6
R
C
D
R
C
D
R
C
D
R
C
D
R
C
D
P
A
S
T
O
Figure 10. UART Receiver Data String
P
R
DATA
FLOW
5
4
T
3
R
2
0
1
S
T
D
7
T
X
D
T
X
D
T
X
6
T
X
D
T
X
D
T
X
D
T
X
D
T
X
D
P
A
S
T
O
Figure 11. UART Transmitter Data String
P
R
DIRECTION
OF DATA
FLOW OUT
OF THE
UT1750AR
Figure 12. The UT1750AR UART Double-Buffered Transmitter Register
REGISTER (OTR) INSTRUCTION
TBR WITH AN OUTPUT
DATA IS LOADED INTO THE
OF THE SYSTEM STATUS
READ FROM BIT 1
TRANSMITTER REGISTER IS
STATUS OF THE UART
8
REGISTER
UART TRANSMITTER
REGISTER (TBR)
UART TRANSMITTER BUFFER
16
DATA BUS
THE UT1750AR’S INTERNAL
FROM BIT 2
TBR IS READ
STATUS OF THE
DATA FLOW
DIRECTION OF
T
R
T
S
0
1
2
3
4
5
6
7
X
T
X
T
X
T
X
T
X
T
X
T
X
T
X
T
R
A
P
O
T
S
0
1
2
3
4
5
6
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
7
D
X
T
D
C
D
C
D
C
D
C
D
C
D
C
D
C
D
C
OF THE SYSTEM
REGISTER
STATUS REGISTER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962R0722402VYC | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 5962R8958702VXA | 5 V FIXED POSITIVE LDO REGULATOR, 1 V DROPOUT, CDSO16 |
| 5962R9215311VTA | 32K X 8 STANDARD SRAM, 55 ns, CDFP36 |
| 5962R9215311VTX | 32K X 8 STANDARD SRAM, 55 ns, CDFP36 |
| 5962G9215309VMX | 32K X 8 STANDARD SRAM, 55 ns, CDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962R0253801VZA | 制造商:Analog Devices 功能描述:- Rail/Tube |
| 5962R0720802VXC | 制造商:Texas Instruments 功能描述:ADS5463 RHA QMLV DEVICE |
| 5962R0722601VZA | 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays |
| 5962R0722701VZA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 50 kSPS-1 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| 5962R0722902VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20 |
發(fā)布緊急采購，3分鐘左右您將得到回復。