參數(shù)資料
型號(hào)： 5962R0150202VYX
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 16 MHz, RISC PROCESSOR, QFP132
封裝： FP-132
文件頁(yè)數(shù)： 7/53頁(yè)
文件大?。?/td> 458K
代理商： 5962R0150202VYX
15
Pop instructions. When the UT1750AR is operating in the RISC
mode, it pre-increments (pops) and post-decrements (pushes)
the SP. In the 1750 mode, the UT1750AR pre-increments (pops)
and post-increments (pushes) the SP.
The programmer accesses the SP by using local I/O commands
to Load and Store the Stack Pointer.
The System Status Register
Figure 8. The System Status Register provides additional status
information on the UT1750AR’s internal signals, including the
status of the internal UART. The bit definitions for STATUS
are given below.
Bit Definitions
All bits in the System Status Register are active high. The values
in the brackets indicate the power-up state.
BIT
NUMBER
MNEMONIC
DESCRIPTION
15
C
Carry. This conditional
status is set if a carry
generated. [0]
14
P
Positive. This conditional
status is set if the result of
operation is positive. [0]
13
Z
Zero. This conditional status
is
set if the result of an operation
is equal to zero. [0]
12
N
Negative. This conditional
status is set if the result of an
operation is negative. [0]
11
V
Overflow. This conditional
status is set when an overflow
condition occurs. [0]
10
J
Normalized. Thisconditional
status is set as the result of a
long instruction. [0]
9
IE
Interrupts enabled. [0]
8
MME
Memory Management
enabled. [0]
7
RE
Receiver Error. This bit is the
logical OR combination of the
OE, FE, and PE status bits.
[0]
6
OE
Overrun Error. When active,
this bit indicates that at least
one data word was lost because
the Data Ready (DR is bit 0
of
the STATUS) signal was
active twice consecutively
without an RBR read. [0]
5
FE
Framing Error. When active,
this bit indicates a stop bit was
missing from the serial
transmission. [0]
4
PE
Parity Error. When active,
this
bit indicates the serial
transmission was received
with
the incorrect parity. [0]
3
CN
MIL-STD-1750A Console
Enabled. When active, this bit
indicates the CONSOLE
discrete input is active.
CONSOLE active sets bit 3 in
the
System Status Register.
2
TBE
UART Transmitter Buffer
Empty. This bit indicates the
Transmitter Buffer Register is
empty and ready for data. [0]
1
TE
UART Transmitter Empty.
This bit is low while the
UART is transmitting data and
goes high when the
transmission is complete. [0]
0
DR
UART Data Ready. This
active-high signal indicates
the
UART received a serial data
word and this data is
available. [0]
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
C
P
Z N V
J
I
M
E
6
O
E
R
E
F
E
P
E
C
N
T
B
E
T
E
D
R
MSB
LSB
Figure 8. The System Status Register (STATUS)
E
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