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參數(shù)資料
| 型號： | 5962R0150202VYX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16 MHz, RISC PROCESSOR, QFP132 |
| 封裝： | FP-132 |
| 文件頁數(shù)： | 51/53頁 |
| 文件大?。?/td> | 458K |
| 代理商： | 5962R0150202VYX |
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7
Test (Input). Asserting this input places the UT1750AR
into a test mode. In this mode, all the UT1750AR’s
outputs, except OSCOUT and SYSCLK, enter a high-
impedance state. When using TEST, the UT1750AR
must have a MRST. MRST must be held active for at
least one SYSCLK period after TEST is
deasserted to assure proper operation (see figure 42b).
TEST is tied to an internal pull-up resistor.
TIMCLK
53
L13
TI
UART CONTROL/TIMER CLOCK
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
CONSOLE
48
N12
TDI
Timer Clock. This 12 MHz clock input generates the baud
rate for the UT1750AR’s internal UART. The input also
provides the clock for the UT1750AR’s two internal MIL-
STD-1750A timers (TIMER A and TIMER B).
Console (Command). Asserting this input sets bit 3 in the
System Status Register. Bit 3 is read with the Input Register
Instruction (INR). When the UT1750AR is operating in the
MIL-STD-1750 mode, asserting CONSOLE during a
Master Reset invokes the maintenance console option. Tied
to an internal pull-down resistor.
TEST
46
P13
TUI
MME
49
N13
TDI
AH
Memory Management Enable. This signal indicates to
the UT1750AR that a Memory Management Unit
(MMU) is present and that the memory management
option is enabled. MME is tied to an internal pull-down
resistor.
AH
AL
PROCESSOR MODE
AS0
104
B7
TTO
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
PS0
108
A4
TTO
AH
Address State. These outputs indicate the current address
state of the UT1750AR. Using these outputs with a
Memory Management Unit (MMU) allows selecting the
MMU’s page register group. These outputs enter a
high-impedance state when the UT1750AR is placed in
the test mode (TEST=0) or during bus cycles not assigned
to this processor.
Processor State. These outputs indicate the current state
of the processor. These outputs enter a high-impedance
state when the UT1750AR is in the test mode (TEST=0)
or during bus cycles not assigned to this processor.
AS1
AS2
AS3
105
106
107
B6
C6
A5
PS1
PS2
PS3
109
110
111
A3
B4
C5
--
Continued from page 6
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