參數(shù)資料
型號(hào)： 5962R0150202VYX
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 16 MHz, RISC PROCESSOR, QFP132
封裝： FP-132
文件頁(yè)數(shù)： 50/53頁(yè)
文件大?。?/td> 458K
代理商： 5962R0150202VYX
6
Output Enable RISC Memory. This signal
allows RISC memory to place data on the RISC instruction
data bus. The Store Register to Instruction Memory (STRI)
instruction removes OE during the CK2 internal clock
cycle. OE enters a high-impedance state when the
UT1750AR is in the test mode (TEST = 0).
AS
115
C3
TTO
OPERAND DATA BUS CONTROL
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
DS
116
B2
TTO
Address Strobe. Indicates a valid address on the Operand
Address bus. UT1750AR places AS in a high-impedance
state when it does not control the Operand busses.
Data Strobe. Indicates valid data is on the Operand Data bus.
The UT1750AR places DS in a high-impedance state when
it does not control the Operand busses.
OE
42
R12
TTO
RISC MEMORY CONTROL
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
WE
43
R13
TTO
Write Enable RISC Memory. This signal allows the
UT1750AR to write to RISC instruction memory. The
Store Register to Instruction Memory (STRI) instruction
asserts WE during the CK2 internal clock cycle. WE
enters a high-impedance state when the UT1750AR is in
the test mode (TEST = 0).
AL
Continued from page 5.
AL
UART CONTROL/TIMER CLOCK
UARTIN
127
F1
TUI
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
UARTOUT
128
G1
TTO
AH
UART Input. The UT1750AR receives serial data
through this input. The serial data is stored in the
UT1750AR’s Receiver Buffer Register (RCVR). It is tied
to an internal pull-up resistor.
UART Output. The serial data stored in the UT1750AR’s
Transmitter Buffer Register (TXMT) is transmitted
through this output. The UART output is fixed at 9600
baud, with eight data bits, odd-parity, and one stop bit.
UARTOUT enters a high-impedance state when the
UT1750AR is in the test mode (TEST=0). (9600 baud @
TIMCLK = 12MHz)
Continued on page 7.
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