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參數(shù)資料
| 型號： | 5962R0150202VYX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16 MHz, RISC PROCESSOR, QFP132 |
| 封裝： | FP-132 |
| 文件頁數(shù)： | 27/53頁 |
| 文件大?。?/td> | 458K |
| 代理商： | 5962R0150202VYX |
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33
0 -
Resume execution with Timers A and Bhalted.
1 -
Resume execution with Timer A on and Timer B off.
2 -
Resume execution with Timer A off and Timer B on.
3 -
Resume execution with Timers A and B on.
Exiting the Console mode
The UT1750AR exits the Console mode of operation by
executing either Continue Execution (C) command or a Run
From Memory Location (R) command. After the UT1750AR
leaves the Console mode, it resumes operating in a normal 1750
mode.
1750 Mode Built-In Test
In the 1750 mode of operation, the UT1750AR features a built-
in test function which executes upon device power-up or reset.
The built-in test function performs “stuck-at” tests on all internal
UT1750AR registers, Timer A, and Timer B. In addition to
testing the UT1750AR registers, the built-in test also checks for
the 1750 emulation code. The 1750 emulation ROM is tested
via a checksum test of all memory locations.
Test failures are recorded in the UT1750AR’s Fault Register.
- UT1750AR failure: Fault Register = 5 (hex)
- Emulation code checksum failure: Fault
Register = 6 (hex)
- Output Discrete 2 (RA17/OD1) = Active
(logic 1)
If the CONSOLE pin is asserted (logic 1) during power-up or
reset, the emulation code will enter the Console mode after
finishing the built-in tests. The Fault Register contents indicate
the failure mode.
A failure in the built-in test without the Console mode
implemented results in Output Discrete 2 (RA17/OD1) being
set to a logic one. In addition to the Output Discrete 2 being set
to a logic one, the UT1750AR will not begin program execution
if failure occurs in PI or FT registers.
1750 XIO
The UT1750AR emulation code does not implement the
following optional XIO command fields and mnemonics:
2008 OD--
Output Discretes
200A RNS-- Reset Normal Power-Up Discrete
4001 CLC--
Clear Console
4003 MPEN-- Memory Protect Enable
50XX LMP -- Load Memory Protect RAM
A001 RIC1-- Read Input/Output Interrupt Code, Level 1
A002 RIC2-- Read Input/Output Interrupt Code, Level 2
A008 RDOR--Read Discrete Output Register
A009 RDI--
Read Discrete Input
A00B TPIO -- Test Programmed Output
D0XX RMP-- Read Memory Protect RAM
The UT1750AR internal UART is I/O mapped as follows:
XIO RA, FFFE (hex)-
RISC Status Register contents
loaded into register RA
XIO RA, FFFF (hex) -
Contents of UART Receiver
Buffer
Register (RCVR) loaded into
register R
XIO RA, 7FFF (hex)-
Contents of register RA
loaded into UART
Transmitter Buffer Register (TBR)
MIL-STD-1750 Console XIO’s result in the following:
1750 INSTRUCTION
EFFECTIVE RESULT
4000 CO
XIO RA, 7FFF (hex)
4001 CLC
NOP
C000 CI
XIO RA, FFFF (hex)
C001 RCS
XIO RA, FFFE (hex)
1750 INSTRUCTION MEMORY MAPPING
The UT1750AR emulates the MIL-STD-1750A ISA by
mapping each of the 1750A opcodes into a specific location
within the UT1750AR’s RISC memory space. This memory
mapping is accomplished by internal UT1750AR hardware. The
memory mapping for the valid 1750 opcodes between 00H and
4FH is shown in table 5.
For the Base Relative and Indexed Base Relative 1750
instructions, the UT1750AR maps multiple instructions to the
same address. The UT1750AR determines the correct operation
for these opcodes by using the Input Register (INR) RISC
instruction. For more information on the operation of the INR
instruction, please refer to the UT1750AR Assembly Language
Manual.
For the remainder of the valid 1750 opcodes between 50H and
FFH, the UT1750AR follows a straightforward memory-
mapping scheme. To determine the RISC memory location for
these 1750 opcodes, the UT1750AR masks off the lower byte
of the instruction and logically shifts the result four times to the
right.
For example, the 1750 opcode for the POPM instruction is
8FxxH. The location of the POPM macro in the UT1750AR’s
RISC memory space is 08F0H.
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