參數(shù)資料
型號： 5962R0150202VYX
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 16 MHz, RISC PROCESSOR, QFP132
封裝： FP-132
文件頁數(shù)： 10/53頁
文件大小： 458K
代理商： 5962R0150202VYX
18
execute a reserved code. [0]
5
PIF
Privileged Instruction Fault.
This bit indicates an attempt
to
execute a privileged
instruction with the Processor
State not equal to zero. [0]
4
ASF
Address State Fault. This bit
indicates an attempt to
establish an Address State
value for an unimplemented
page register set. [0]
3
Reserved.
2
BITF
Built-In-Test Fault. This bit
indicates the UT1750AR has
detected a hardware built-in-
test
error. [0]
1 - 0
Spare BIT. The user defines
these bits as additional BIT
parameters. [0]
The Interrupt Mask Register (MK)
The Interrupt Mask Register (MK) (figure 16) contains one
mask bit for each of the 16 system interrupts. All bits in the MK
are set or reset under software control, although setting bits 15
and 10, Power Down Interrupt and Executive Call respectively,
has no effect on the UT1750AR’s operation because these
interrupts cannot be masked. The UT1750AR reads or loads the
MK with RISC I/O instructions.
The 1750 Status Word Register (SW)
The MIL-STD-1750A Instruction Set Architecture (ISA)
defines the Status Word Register (SW). The UT1750AR reads
and loads the SW with RISC I/O instructions. Figure 17 shows
the definitions of various bits in the SW.
Bit Definitions
BIT
NUMBER
MNEMONIC
DESCRIPTION
15
C
Carry. This bit is set if the
result of an addition operation
generates a carry or if the
result
of a subtraction generates no
borrow.
14
P
Positive. This bit is set if the
result of an operation is
greater than zero.
13
Z
Zero. This bit is set if the
result of an operation is equal
to zero.
12
N
Negative. This bit is set if the
result of an operation is less
than zero.
11 - 8
Reserved Bits.
7 - 4
PS3 -
Processor State. This PS0four
bit field determinesthe legal
illegal criteriafor privileged
instructions.
3 - 0
AS3 -
Address State. Used in AS0
conjunction with the optional
UT1750 MMUMemory
Management Unit, this four-
bit
field determines the current
extended address page.
Note: If condition codes are turned on (default after reset) the
condition codes reflect the corresponding bits in the STATUS
register.
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
P
W
D
N
M
C
H
E
I
N
T
O
F
L
P
O
F
I
P
O
E
X
C
L
F
L
P
T
I
M
6
T
I
M
I
N
T
I
N
T
I
N
T
I
O
L
I
N
T
I
O
L
I
N
T
MSB
LSB
Figure 16. The Interrupt Mask Register (MK)
U
A
B
1
2
3
1 4
2 5
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
CONDITION RESERVED
6
PROCESSOR ADDRESS
MSB
LSB
Figure 17. The 1750 Status Register (SW)
STATUS
STATE
(CS)
(PS)
(AS)
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