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參數(shù)資料
| 型號： | 30044-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible with MMX Support 32-Bit Geode GXm Processor(低功耗集成兼容X86帶有MMX的32位 Geode GXm技術(shù)處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁數(shù)： | 180/244頁 |
| 文件大小： | 4496K |
| 代理商： | 30044-23 |
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180
Revision 3.1
Power Management (
Continued
)
G
Table 6-2. Power Management Control and Status Registers
Bit
Name
Description
GX_BASE+8500h-8503h
PM_STAT_SMI Register (R/W)
Default Value = xxxxxx00h
31:8
7:3
2
RSVD
RSVD
SMI_MEM
Reserved
— These bits are not used. Do not write to these bits.
Reserved
— Set to 0.
SMI VGA Emulation Memory
— This bit is set high if a SMI was generated for VGA emulation in
response to a VGA memory access. An SMI can be generated on a memory access to one of three
regions in the A0000h-to-BFFFFh range as specified in the BC_XMAP_1 register.
SMI VGA Emulation I/O
— This bit is set high if a SMI was generated for VGA emulation in
response to an I/O access. An SMI can be generated on a I/O access to one of three regions in the
3B0h-to-3DFh range as specified in the BC_XMAP_1 register.
SMI Pin
— When set high, this bit indicates that the SMI# input pin has been asserted to the
GXm processor.
Note:
These bits are “sticky” bits and can only be cleared with a write of ‘1’ to the respective bit.
1
SMI_IO
0
SMI_PIN
GX_BASE+8504h-8507h
PM_CNTRL_TEN Register (R/W)
Default Value = xxxxxx00h
31:8
7:6
5
RSVD
RSVD
Reserved
— These bits are not used. Do not write to these bits.
Reserved
— Set to 0.
Transmission Test (Write Only)
— Setting this bit causes the GXm processor to immediately trans-
mit the current contents of the serial packet. This bit is write only and is used primarily for test. This
bit returns 0 on a read.
Transmission Frequency
— This field indicates the time between serial packet transmissions.
Serial packet transmissions occur at the selected interval only if at least one of the packet bits is set
high: 00 = Disable transmitter; 01 = 1 ms; 10 = 5 ms; 11 = 10 ms.
CPU Activity Read Enable
— Setting this bit high enables reporting of CPU Level-1 cache read
misses that are not a result of an instruction fetch. This bit is a don’t-care if the CMEN bit is not set
high
CPU Activity Master Enable
— Setting this bit high enables reporting of CPU Level-1 cache
misses in bit 6 of the serial transmission packet. When enabled, the CPU Level-1 cache miss activity
is reported on any read (assuming the CREN is set high) or write access excluding misses that
resulted from an instruction fetch.
Video Event Enable
— Setting this bit high enables video decode events to be reported in bit 0 of
the serial transmission packet. CPU or graphics-pipeline accesses to the graphics memory and dis-
play-controller-register accesses are also reported.
X_TEST (WO)
4:3
X_FREQ
2
CPU_RD
1
CPU_EN
0
VID_EN
GX_BASE+8508h-850Bh
PM_CNTRL_CSTP Register (R/W)
Default Value = xxxxxx00h
31:8
7:1
0
RSVD
RSVD
CLK_STP
Reserved
— These bits are not used. Do not write to these bits.
Reserved
— Set to 0.
Clock Stop
— This bit configures the GXm processor for Suspend Refresh Mode or 3-Volt Suspend
Mode:
0 = Suspend Refresh Mode. The clocks to the memory and display controller are active.
1 = 3-Volt Suspend Mode. All internal clocks are stopped.
Note:
When this register is set high and the Suspend input pin (SUSP#) is asserted, the GXm processor stops all it’s internal clocks,
and asserts the Suspend Acknowledge output pin (SUSPA#). Once SUSPA# is asserted the GXm processor’s SYSCLK input
can be stopped. If this register is cleared, the internal memory-controller and display-controller clocks are not stopped on the
SUSP#/SUSPA# sequence, and the SYSCLK input can not be stopped.
GX_BASE+850Ch-850Fh
PM_SER_PACK Register (R/W)
Default Value = xxxxxx00h
31:8
7
RSVD
VID_IRQ
Reserved
— These bits are not used. Do not write to these bits.
Video IRQ
— This bit indicates the occurrence of a video vertical sync pulse. This bit is set at the
same timer that the VINT (Vertical Interrupt) bit is set in the DC_TIMING_CFG register. The VINT bit
has a corresponding enable bit (VIEN) in the DC_TIM_CFG register.
CPU Activity
— This bit indicates the occurrence of a level 1 cache miss that was not a result of an
instruction fetch. This bit has a corresponding enable bit in the PM_CNTL_TEN register.
Reserved
— Set to 0.
Programmable Address Decode
— This bit indicates the occurrence of a programmable memory
address decode. This bit is set based on the values of the PM_BASE register and the PM_MASK
register. The PM_BASE register can be initialized to any address in the full 128 MB address range.
6
CPU_ACT
5:2
1
RSVD
USR_DEF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3004430 | 功能描述:DIN導(dǎo)軌式接線端子 UK 5-MTK RoHS:否 制造商:Phoenix Contact 類型:Feed Through Modular Terminal Block 位置/觸點數(shù)量:1 線規(guī)量程:26-14 電流額定值:5 A, 15 A 電壓額定值:300 V, 600 V 安裝風(fēng)格: 端接類型:Push-In |
| 30044-44L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 70MM |
| 3004472 | 制造商:Phoenix Contact 功能描述:UK 5-HESI (5X20) |
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| 300449 | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:HAND TOOL ASSEMBLY |
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