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參數(shù)資料
| 型號(hào)： | 30044-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible with MMX Support 32-Bit Geode GXm Processor(低功耗集成兼容X86帶有MMX的32位 Geode GXm技術(shù)處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁數(shù)： | 142/244頁 |
| 文件大小： | 4496K |
| 代理商： | 30044-23 |
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142
Revision 3.1
Integrated Functions (
Continued
)
G
9
CVSP
CRT Vertical Sync Polarity
:
0 = Causes CRT VSYNC signal to be normally low, generating a high pulse during the retrace interval.
1 = Cause CRT VSYNC signal to be normally high, generating a low pulse during the retrace interval.
CRT Horizontal Sync Polarity
:
0 = Causes CRT HSYNC signal to be normally low, generating a high pulse during the retrace interval.
1 = Causes CRT HSYNC signal to be normally high, generating a low pulse during the retrace interval.
Blink Enable:
Blink circuitry: 0 = Disable; 1 = Enable.
If enabled, the hardware cursor will blink as well as any pixels. This is provided to maintain compatibility
with VGA text modes. The blink rate is determined by the bit 16 (BKRT).
Vertical Interrupt Enable:
Generate a vertical interrupt on the occurrence of the next vertical sync pulse:
0 = Disable, vertical interrupt is cleared;
1 = Enable.
This bit is provided to maintain backward compatibility with the VGA.
Timing Generator Enable:
Allow timing generator to generate the timing control signals for the display.
0 = Disable, the Timing Registers may be reprogrammed, and all circuitry operating on the DOTCLK will be
reset.
1 = Enable, no write operations are permitted to the Timing Registers.
DDC Clock:
This bit is used to provide the serial clock for reading the DDC data pin. This bit is multiplexed
onto the CRTVSYNC pin, but in order for it to have an effect, the VSYE bit must be set low to disable the
normal vertical sync. Software should then pulse this bit high and low to clock data into the GXm proces-
sor.
This feature is provided to allow support for the VESA Display Data Channel standard level DDC1.
Blank Enable:
Allow generation of the composite blank signal to the display device:
0 = Disable; 1 = Enable.
When disabled, the BLANK# output will be a static low level. This allows VESA DPMS compliance.
Horizontal Sync Enable:
Allow generation of the horizontal sync signal to a CRT display device:
0 = Disable; 1 = Enable.
When disabled, the HSYNC output will be a static low level. This allows VESA DPMS compliance.
Note that this bit only applies to the CRT; the flat panel HSYNC is controlled by the automatic power
sequencing logic.
Vertical Sync Enable:
Allow generation of the vertical sync signal to a CRT display device:
0 = Disable; 1 = Enable.
When disabled, the VSYNC output will be a static low level. This allows VESA DPMS compliance.
Note that this bit only applies to the CRT; the flat panel VSYNC is controlled by the automatic power
sequencing logic.
Flat Panel Power Enable:
On a low-to-high transition this bit will enable the flat panel power-up sequence
to begin. This will first turn on VDD to the panel, then start the clocks, syncs, and pixel bus, then turn on
the LCD bias voltage, and finally the backlight.
On a high-to-low transition, this bit will disable the outputs in the reverse order.
8
CHSP
7
BLNK
6
VIEN
5
TGEN
4
DDCK
3
BLKE
2
VSYE
1
HSYE
0
FPPE
GX_BASE+830Ch-830Fh
DC_OUTPUT_CFG Register (R/W)
Default Value = xxx00000h
31:16
15
RSVD
DIAG
Reserved:
Set to 0.
Compressed Line Buffer Diagnostic Mode:
This bit will allow testability of the Compressed Line Buffer
via the diagnostic access registers. A low-to-high transition will reset the Compressed Line Buffer write
pointer. 0 = Disable (Normal operation); 1 = Enable.
Compressed Line Buffer Read/Write Select:
Enables the read/write address to the Compressed Line
Buffer for use in diagnostic testing of the RAM.
0 = Write address enabled
1 = Read address enabled
Panel Data Enable High:
0 = The PANEL[17:9] data bus to be driven to a logic low level to effectively blank an attached flat panel
display or disable the upper pixel data bus for 16-bit pixel port RAMDACs.
1 = If no flat panel is attached, the PANEL[17:9] data bus will be driven with active pixel data. If a flat panel
is attached, setting this bit high will have no effect
the upper panel bus will be driven based upon the
power sequencing logic.
14
CFRW
13
PDEH
Table 4-30. Display Controller Configuration and Status Registers (Continued)
Bit
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 30046-23 | Low Power Integrated x86-Compatible 32-Bit Geode GXLV Processor(低功耗集成兼容X86的32位 Geode GXLV技術(shù)處理器) |
| 300471U | Radial, -55dotc, long life wsitching-power |
| 300CNQ | SCHOTTKY RECTIFIER |
| 300CNQ035 | SCHOTTKY RECTIFIER |
| 300CNQ040 | SCHOTTKY RECTIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3004430 | 功能描述:DIN導(dǎo)軌式接線端子 UK 5-MTK RoHS:否 制造商:Phoenix Contact 類型:Feed Through Modular Terminal Block 位置/觸點(diǎn)數(shù)量:1 線規(guī)量程:26-14 電流額定值:5 A, 15 A 電壓額定值:300 V, 600 V 安裝風(fēng)格: 端接類型:Push-In |
| 30044-44L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 70MM |
| 3004472 | 制造商:Phoenix Contact 功能描述:UK 5-HESI (5X20) |
| 300448 | 功能描述:手工工具 RETAINING PIN RoHS:否 制造商:Molex 產(chǎn)品:Extraction Tools 類型: 描述/功能:Extraction tool |
| 300449 | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:HAND TOOL ASSEMBLY |
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