- 您現(xiàn)在的位置：買賣IC網 > PDF目錄371436 > 28F640J3C-120 (Intel Corp.) Intel StrataFlash Memory (J3) PDF資料下載
參數(shù)資料
| 型號： | 28F640J3C-120 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 38/72頁 |
| 文件大?。?/td> | 905K |
| 代理商： | 28F640J3C-120 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
256-Mbit J3 (x8/x16)
38
Datasheet
To perform a page mode read after any other operation, the Read Array command must be issued to
read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used
to access register information. During register access, only one word is loaded into the page buffer.
10.1.2
Enhanced Configuration Register (ECR)
The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed to
by the Set Enhanced Configuration Register command, and can select between Four-Word Page
mode and Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when
RP# is deasserted or power is removed from the device. To modify ECR settings, use the Set
Enhanced Configuration Register command. The Set Enhanced Configuration Register command
is written along with the configuration register value, which is placed on the lower 16 bits of the
address bus A[15:0]. This is followed by a second write that confirms the operation and again
presents the enhanced configuration register data on the address bus. After executing this
command, the device returns to Read Array mode. The ECR is shown in
Table 15, “Enhanced
Configuration Register” on page 38
.
Note:
For forward compatibility reasons, if the 8-word Asynchronous Page mode is to be used on J3C, a
Clear Status Register command must be issued after issuing the Set Enhanced Configuration
Register command. See
Table 16, “J3C Asynchronous 8-Word Page Mode Command Bus-Cycle
Definition” on page 38
for further details.
NOTE:
Any reserved bits should be set to 0.
NOTE:
X = Any valid address within the device. ECD = Enhanced Configuration Register Data.
Table 15. Enhanced Configuration Register
Res.
Reserved
R
R
8W
R
R
R
R
R
R
R
R
R
R
R
R
R
ECR
.15
ECR
.14
ECR
.13
ECR
.12
ECR
.11
ECR
.10
ECR
.9
ECR
.8
ECR
.7
ECR
.6
ECR
.5
ECR
.4
ECR
.3
ECR
.2
ECR
.1
ECR
.0
BITS
DESCRIPTION
NOTES
ECR[15:14]
Reserved
Reserved for Future Use. Set to 0 until further
notice.
ECR[13]
“1” = 8Word Page mode
“0” = 4Word Page mode
ECR[12:0]
Reserved
Reserved for Future Use. Set to 0 until further
notice.
Table 16. J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Command
Bus
Cycles
Req’d.
First Bus Cycle
Second Bus Cycle
Third Bus Cycle
Oper
Addr
(1)
Data
Oper
Addr
(1)
Data
Oper
Addr
(1)
Data
Set Enhanced
Configuration Register
(Set ECR)
3
Write
ECD
0x60
Write
ECD
0x04
Write
X
0x50
相關PDF資料 |
PDF描述 |
|---|---|
| 28LV64A | 64K (8K x 8) Low Voltage CMOS EEPROM(低壓,64K位, CMOS 并行EEPROM) |
| 28M0U | 60V 300mA MONOLITHIC DIODE ARRAY |
| 28M0DC | 60V 300mA MONOLITHIC DIODE ARRAY |
| 28M0DS | 60V 300mA MONOLITHIC DIODE ARRAY |
| 28M0UC | 60V 300mA MONOLITHIC DIODE ARRAY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640J3D75 | 制造商:Intel 功能描述: 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F640J5 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 Volt Intel StrataFlash? Memory |
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| 28F640L30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復。