參數(shù)資料
型號: 28F640J3A
廠商: Intel Corp.
英文描述: 3 Volt Intel StrataFlash Memory(3 V 64M位英特爾StrataFlash存儲器)
中文描述: 3伏特英特爾StrataFlash存儲器(3伏6400位英特爾的StrataFlash存儲器)
文件頁數(shù): 32/58頁
文件大?。?/td> 574K
代理商: 28F640J3A
28F128J3A, 28F640J3A, 28F320J3A
26
PRODUCT PREVIEW
4.15.3
LOCKING THE PROTECTION REGISTER
The user-programmable segment of the protection register is lockable by programming Bit 1 of the
PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the
unique device number. Bit 1 is set using the Protection Program command to program “FFFD” to
the PR-LOCK location. After these bits have been programmed, no further changes can be made to
the values stored in the protection register. Protection Program commands to a locked section will
result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1).
Protection register lockout state is not reversible.
OTP_MAP
NOTE:
A
is not used in x16 mode when accessing the protection register map (See Table 20 for x16
addressing). For x8 mode A
0
is used (See Table 21 for x8 addressing).
Figure 6. Protection Register Memory Map
4 Words
Factory Programmed
4 Words
User Programmed
1 Word Lock
88H
85H
84H
81H
80H
Word
Address
A[23 - 1]: 128 Mbit
A[22 - 1]: 64 Mbit
A[21 - 1]: 32 Mbit
Table 16. Read Configuration Register Definition
RM
R
R
R
R
R
R
R
16 (A
16
)
15
14
13
12
11
10
9
R
R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
NOTES:
RCR.16 = READ MODE (RM)
0 = Standard Word/Byte Reads Enabled (Default)
1 = Page-Mode Reads Enabled
Read mode configuration effects reads from the flash array.
Status register, query, and identifier reads support standard
word/byte read cycles.
RCR.15–1 = RESERVED FOR FUTURE ENHANCEMENTS (R)
These bits are reserved for future use. Set these bits to “0.”
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