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參數(shù)資料
| 型號： | 28F640J3A |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory(3 V 64M位英特爾StrataFlash存儲器) |
| 中文描述： | 3伏特英特爾StrataFlash存儲器（3伏6400位英特爾的StrataFlash存儲器） |
| 文件頁數(shù)： | 30/58頁 |
| 文件大?。?/td> | 574K |
| 代理商： | 28F640J3A |
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28F128J3A, 28F640J3A, 28F320J3A
24
PRODUCT PREVIEW
4.12
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once
the STS pin has been configured, it remains in that configuration until another configuration
command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation
where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state
machine is ready for a new operation or suspended. Table 17 displays the possible STS
configurations.
To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed
by the desired configuration code. The three alternate configurations are all pulse mode for use as a
system interrupt as described below. For these configurations, bit 0 controls Erase Complete
interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h
configuration code with the Configuration command resets the STS pin to the default RY/BY#
level mode. The possible configurations and their usage are described in Table 17. The
Configuration command may only be given when the device is not busy or suspended. Check SR.7
for device status. An invalid configuration code will result in both status register bits SR.4 and
SR.5 being set to “1.” When configured in one of the pulse modes, the STS pin pulses low with a
typical pulse width of 250 ns.
4.13
Set Block Lock-Bit Commands
A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits
gate program and erase operations. Individual block lock-bits can be set using the Set Block Lock-
Bit command. This command is invalid while the WSM is running or the device is suspended.
Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with
appropriate block address is followed by either the set block lock-bit confirm (and an address
within the block to be locked). The WSM then controls the set lock-bit algorithm. After the
sequence is written, the device automatically outputs status register data when read (see Figure 12).
The CPU can detect the completion of the set lock-bit event by analyzing the STS pin output or
status register bit SR.7.
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared. The CUI will remain in read status register mode
until a new command is issued.
This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally
set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being
set to “1.” Also, reliable operations occur only when V
CC
and V
PEN
are valid. With V
PEN
≤
V
PENLK
,
lock-bit contents are protected against alteration.
4.14
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock-
bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while
the WSM is running or the device is suspended.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F128 | 3 Volt Intel StrataFlash Memory |
| 28F1602C3 | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 28F3204C3 | 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級堆芯片封裝存儲器) |
| 28F1604C3 | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 28F160C18 | 1.8V Advanced+ Boot Block Flash Memory(1.8V高級引導(dǎo)塊閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640J3C120 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F640J3C-120 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F640J3D75 | 制造商:Intel 功能描述: 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F640J5 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 Volt Intel StrataFlash? Memory |
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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