參數(shù)資料
型號： 28F640J3A
廠商： Intel Corp.
英文描述： 3 Volt Intel StrataFlash Memory(3 V 64M位英特爾StrataFlash存儲器)
中文描述： 3伏特英特爾StrataFlash存儲器（3伏6400位英特爾的StrataFlash存儲器）
文件頁數(shù)： 17/58頁
文件大?。?/td> 574K
代理商： 28F640J3A
28F128J3A, 28F640J3A, 28F320J3A
PRODUCT PREVIEW
11
NOTES:
1. Refer to DC Characteristics When V
≤
V
, memory contents can be read, but not altered.
2. X can be V
or V
IH
for control and address pins, and V
PENLK
or V
PENH
for V
PEN
. See DC Characteristics for V
PENLK
and V
voltages.
3. In default mode, STS is V
when the WSM is executing internal block erase, program, or lock-bit
configuration algorithms. It is V
when the WSM is not busy, in block erase suspend mode (with
programming inactive), program suspend mode, or reset/power-down mode.
4. See Read Identifier Codes Command section for read identifier code data.
5. See Read Query Mode Command section for read query data.
6. Command writes involving block erase, program, or lock-bit configuration are reliably executed when V
PEN
=
V
and V
is within specification.
7. Refer to Table 4 for valid D
during a write operation.
8. DQ refers to DQ
0–
DQ
if BYTE# is low and DQ
DQ
15
if BYTE# is high.
9. High Z will be V
with an external pull-up resistor.
10.See Table 2 for valid CE configurations.
11.OE# and WE# should never be enabled simultaneously.
Table 3. Bus Operations
Mode
Notes
RP#
CE
0,1,2
(10)
OE#
(11)
WE#
(11)
Address
V
PEN
DQ
(8)
STS
(default
mode)
Read Array
1,2,3
V
IH
Enabled
V
IL
V
IH
X
X
D
OUT
High Z
(9)
Output Disable
V
IH
Enabled
V
IH
V
IH
X
X
High Z
X
Standby
V
IH
Disabled
X
X
X
X
High Z
X
Reset/Power-Down Mode
V
IL
X
X
X
X
X
High Z
High Z
(9)
Read Identifier Codes
V
IH
Enabled
V
IL
V
IH
See
Figure 5
X
Note 4
High Z
(9)
Read Query
V
IH
Enabled
V
IL
V
IH
See
Table 7
X
Note 5
High Z
(9)
Read Status (WSM off)
V
IH
Enabled
V
IL
V
IH
X
X
D
OUT
Read Status (WSM on)
V
IH
Enabled
V
IL
V
IH
X
V
PENH
DQ
7
= D
OUT
DQ
15–8
= High Z
DQ
6–0
= High Z
Write
3,6,7
V
IH
Enabled
V
IH
V
IL
X
X
D
IN
X
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