- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371435 > 28F320C3 (INTEL CORP) 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | 28F320C3 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器) |
| 中文描述： | 32M X 8 FLASH 3V PROM |
| 文件頁數(shù)： | 14/59頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 28F320C3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
28F800C3, 28F160C3, 28F320C3
E
14
PRELIMINARY
3.2.5
PROGRAM MODE
Programming is executed using a two-write
sequence. The Program Setup command (40H) is
written to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM will execute a sequence of internally
timed events to program desired bits of the
addressed location, then verify the bits are
sufficiently programmed. Programming the memory
results in specific bits within an address location
being changed to a
“0.” If the user attempts to
program “1”s, the memory cell contents do not
change and no error occurs.
The status register indicates programming status:
while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling
either CE# or OE#. While programming, the only
valid commands are Read Status Register,
Program Suspend, and Program Resume.
When programming is complete, the program status
bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status
register is set to indicate a program failure. If SR.3
is set then V
PP
was not within acceptable limits, and
the WSM did not execute the program command. If
SR.1 is set, a program operation was attempted on
a locked block and the operation was aborted.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, to prevent inadvertent status register
reads, be sure to reset the CUI to read array mode.
3.2.5.1
Suspending and Resuming
Program
The Program Suspend command halts an in
-
progress program operation so that data can be
read from other locations of memory. Once the
programming process starts, writing the Program
Suspend command to the CUI requests that the
WSM
suspend
the
program
predetermined points in the program algorithm).
The device continues to output status register data
after the Program Suspend command is written.
Polling status register bits SR.7 and SR.2 will
determine when the program operation has been
suspended (both will be set to “1”). t
WHRH1
/t
EHRH1
specify the program suspend latency.
sequence
(at
A Read Array command can now be written to the
CUI to read data from blocks other than that which
is suspended. The only other valid commands while
program is suspended are Read Status Register,
Read Configuration, Read Query, and Program
Resume. After the Program Resume command is
written to the flash memory, the WSM will continue
with the programming process and status register
bits SR.2 and SR.7 will automatically be cleared.
The device automatically outputs status register
data when read (see Figure 12 in Appendix B,
Program Suspend/Resume Flowchart
) after the
Program Resume command is written. V
PP
must
remain at the same V
PP
level used for program
while in program suspend mode. RP# must also
remain at V
IH
.
3.2.6
ERASE MODE
To erase a block, write the Erase Set
-
up and Erase
Confirm commands to the CUI, along with an
address identifying the block to be erased. This
address is latched internally when the Erase
Confirm command is issued. Block erasure results
in all bits within the block being set to “1.” Only one
block can be erased at a time. The WSM will
execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits
within the block to “1,” then verify that all bits within
the block are sufficiently erased. While the erase
executes, status bit 7 is a “0.”
When the status register indicates that erasure is
complete, check the erase status bit to verify that
the erase operation was successful. If the Erase
operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase
failure. If V
was not within acceptable limits after
the Erase Confirm command was issued, the WSM
will not execute the erase sequence; instead, SR.5
of the status register is set to indicate an erase
error, and SR.3 is set to a “1” to identify that V
PP
supply voltage was not within acceptable limits.
After an erase operation, clear the status register
(50H) before attempting the next operation. Any
CUI instruction can follow after erasure is
completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in
read array mode after the erase is complete.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F800C3 | 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器) |
| 28F160C3 | 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器) |
| 28F320D18 | 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器) |
| 28F320J5 | 5 Volt Intel StrataFlash Memory(5 V 32M位英特爾StrataFlash存儲(chǔ)器) |
| 28F640J5 | 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F320J3D75 | 制造商:undefined 功能描述: |
| 28F320J5 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT |
| 28F320J5_02 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 Volt Intel StrataFlash? Memory |
| 28F320S3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| 28F320S5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。