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| 型號： | 272420-007 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel386 EX Embedded Microprocessor |
| 中文描述： | 英特爾386防爆嵌入式微處理器 |
| 文件頁數(shù)： | 49/56頁 |
| 文件大小： | 766K |
| 代理商： | 272420-007 |
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Intel386 EX Embedded Microprocessor
Datasheet
49
Figure 22. Pipelined Address Cycle
A2477-03
LOCK#
D15:0
Valid 2
Valid 3
Valid 4
CLK2
BHE#, BLE#, A25:1,
M/IO#, D/C#
Valid3
Valid4
Valid2
Valid1
W/R#
ADS#
NA#
T1P
T2P
T2P
T1P
T2
T2P
T1P
T2i
T2P
T1P
Cycle 1
Pipelined
(Write)
[Late Ready]
Cycle 2
Non-pipelined
(Read)
Cycle 3
Pipelined
(Write)
[Late Ready]
Cycle 4
Pipelined
(Read)
CLKOUT
ADS# is asserted as
soon as the CPU has
another bus cycle to
perform, which is not
always immediately
after NA# is asserted.
As long as the CPU enters the T2P
state during Cycle 3, address
pipelining is maintained in Cycle 4.
Note ADS# is
asserted in
every T2P state.
In
2
Asserting NA# more
than once during
any cycle has no
additional effects
NA# could have been asserted in T1P
if desired. Assertion now is the latest
time possible to allow the CPU to enter
T2P state to maintain pipelining in cycle 3.
READY#
RD#
WR#
LBA#
BS8#
Out 1
Out
Valid 1
Out 3
T2
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