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| 型號(hào)： | 272420-007 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel386 EX Embedded Microprocessor |
| 中文描述： | 英特爾386防爆嵌入式微處理器 |
| 文件頁數(shù)： | 40/56頁 |
| 文件大小： | 766K |
| 代理商： | 272420-007 |
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Intel386 EX Embedded Microprocessor
40
Datasheet
t
103
STXCLK, SRXCLK High Time
7CLK2/
2
7CLK2/
2
(2)
t
104
STXCLK Low to SSIOTX
Delay
3CLK2
3CLK2
t
105
SSIORX to SRXCLK High
Setup Time
0
0
(2)
t
106
SSIORX from SRXCLK Hold
Time
3CLK2
3CLK2
Timer Control Unit (TCU) Inputs
t
107
t
108
t
109
t
110
t
111
TMRCLKnFrequency
8
8
(Unit is MHz)
TMRCLKnLow
60
60
TMRCLKnHigh
60
60
TMRGATEn High Width
50
50
TMRGATEn Low Width
50
50
t
112
TMRGATEn to TMRCLK
Setup Time (external
TMRCLK only)
10
15
t
112a
TMRGATEn to TMRCLK Hold
Time (external TMRCLK only)
19
19
Timer Control Unit (TCU) Outputs
t
113
TMRGATEn Low to TMROUT
Valid
44
52
t
114
TMRCLKnLow to TMROUT
Valid
48
52
Table 12. 3-Volt AC Characteristics (Sheet 4 of 5)
Symbol
Parameter
25 MHz
3.0 V to 3.6 V
20 MHz
2.7 V to 3.6 V
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I
LO
in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
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