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參數(shù)資料
| 型號： | 272420-007 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel386 EX Embedded Microprocessor |
| 中文描述： | 英特爾386防爆嵌入式微處理器 |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 766K |
| 代理商： | 272420-007 |
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Intel386 EX Embedded Microprocessor
30
Datasheet
6.3
AC Specifications
Table 11 lists output delays, input setup requirements, and input hold requirements for the 5 V
EXTC processor; Table 12 is for the EXTB processor. All AC specifications are relative to the
CLK2 rising edge crossing the V
CC
/2 level for the EXTB, or 2.0 Volts for the EXTC.
Figures 8 and 9 show the measurement points for AC specifications for the EXTB and EXTC
processors. Inputs must be driven to the indicated voltage levels when AC specifications are
measured. Output delays are specified with minimum and maximum limits measured as shown.
The minimum delay times are hold times provided to external circuitry. Input setup and hold times
are specified as minimums, defining the smallest acceptable sampling window. Within the
sampling window, a synchronous input signal must be stable for correct operation.
Outputs ADS#, W/R#, CS5:0#, UCS#, D/C#, M/IO#, LOCK#, BHE#, BLE#, REFRESH#/CS6#,
READY#, LBA#, A25:1, HLDA and SMIACT# change only at the beginning of phase one. D15:0
(write cycles) and PWRDOWN change only at the beginning of phase two. RD# and WR# change
to their active states at the beginning of phase two. RD# changes to its inactive state (end of cycle)
at the beginning of phase one. See the
Intel386 EX Embedded Microprocessor User's Manual
for
a detailed explanation of early READY# vs. late READY#.
The READY#, HOLD, BUSY#, ERROR#, PEREQ, BS8#, and D15:0 (read cycles) inputs are
sampled at the beginning of phase one. The NA#, SMI#, and NMI inputs are sampled at the
beginning of phase two.
Figure 8. Drive Levels and Measurement Points for AC Specifications (EXTC)
A
B
Tx
Valid
Output n+1
a
a
c
c
b
Min
Max
C
D
CLK2
OUTPUTS
(A25:1,BHE#
BLE#,ADS#,M/IO#
D/C#W/R#,LOCK#
HLDA, SMIACT#)
OUTPUTS
(D15:0)
INPUTS
(N/A#,INTR
NMI,SMI#)
INPUTS
(READY#,HOLD
FLT#,ERROR#
BUSY#,PEREQ
D15:0,A20)
LEGEND
a -
V
/2
b - 2.0V
c = 1.5V
A - Maximum Output Delay Spec
B - Minimum Output Delay Spec
C - Minimum Input Setup Spec
D - Minimum Input Hold Spec
PH1
PH2
3.0V
0V
Valid
Output n
A
B
Valid
Output n+1
a
a
Min
Max
Valid
Output n
Valid
Input
c
c
C
D
3.0V
0V
Valid
Input
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