
Intel386 EX Embedded Microprocessor
Datasheet
41
Interrupt Control Unit (ICU) Inputs
t
115
D7:0 Setup Time
(INTA# Cycle 2)
9
11
t
116
D7:0 Hold Time
(INTA# Cycle 2)
6
6
Interrupt Control Unit (ICU) Outputs
t
117
DMA Unit Inputs
CLK2 High to CAS2:0 Valid
36
46
t
118
DREQ Setup Time
(Sync Mode)
19
21
t
119
DREQ Hold Time
(Sync Mode)
4
4
(2)
t
120
DREQ Setup Time
(Async Mode)
11
11
t
121
DREQ Hold Time
(Async Mode)
11
11
(2)
t
122
EOP# Setup Time
(Sync Mode)
17
21
t
123
EOP# Hold Time
(Sync Mode)
4
4
t
124
EOP# Setup Time
(Async Mode)
11
11
t
125
EOP# Hold Time
(Async Mode)
11
11
DMA Unit Outputs
t
126
t
127
t
128
JTAG Test-logic Unit
DACK# Output Valid Delay
4
31
4
33
EOP# Active Delay
4
27
4
33
EOP# Float Delay
4
27
4
33
(3)
t
129
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I
LO
in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
TCK Frequency
10
10
(Unit is MHz)
Table 12. 3-Volt AC Characteristics (Sheet 5 of 5)
Symbol
Parameter
25 MHz
3.0 V to 3.6 V
20 MHz
2.7 V to 3.6 V
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)