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參數(shù)資料
| 型號： | 272420-007 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel386 EX Embedded Microprocessor |
| 中文描述： | 英特爾386防爆嵌入式微處理器 |
| 文件頁數(shù)： | 34/56頁 |
| 文件大?。?/td> | 766K |
| 代理商： | 272420-007 |
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Intel386 EX Embedded Microprocessor
34
Datasheet
t
43
D15:0 Output Valid to WR# High
2CLK2
–10
2CLK2
– 10
(5)
t
44
D15:0 Output Hold After WR# High
CLK2
–10
CLK2
–10
t
45
WR# High to D15:0 Float
CLK2
+ 10
CLK2
+ 10
(3)
t
46
WR# Pulse Width
2CLK2
–10
2CLK2
–10
(7)
t
47
A25:1, BHE#, BLE# Valid to D15:0
Valid
4CLK2 -
28
4CLK2-
31
(5)
t
47a
UCS#, CS6:0# Valid to D15-D0
Valid
4CLK2 -
31
4CLK2 -
35
(5)
t
48
RD# Low to D15:0 Input Valid
3CLK2 –
25
3CLK2 –
29
(5)
t
49
t
50
D15:0 Hold After RD# High
0
0
RD# High to D15:0 Float
CLK2
CLK2
(3)
t
51
A25:1, BHE#, BLE# Hold After
RD# High
0
0
t
51a
UCS#, CS6:0# Hold after RD#
High
0
0
t
52
RD# Pulse Width
3CLK2
–10
3CLK2
–10
Synchronous Serial I/O (SSIO) Unit
t
100
STXCLK, SRXCLK Frequency
(Master Mode)
CLK2/8
CLK2/8 (Unit is MHz)
t
101
STXCLK, SRXCLK Frequency
(Slave Mode)
CLK2/8
CLK2/8 (Unit is MHz)
t
102
t
103
t
104
STXCLK, SRXCLK Low Time
7CLK2/2
7CLK2/2
(2)
STXCLK, SRXCLK High Time
7CLK2/2
7CLK2/2
(2)
STXCLK Low to SSIOTX Delay
3CLK2
3CLK2
t
105
SSIORX to SRXCLK High Setup
Time
0
0
(2)
t
106
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I
LO
in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
SSIORX from SRXCLK Hold Time
3CLK2
3CLK2
Table 11. 5-Volt AC Characteristics (Sheet 3 of 5)
Symbol
Parameter
33 MHz
25 MHz
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
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