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參數(shù)資料
| 型號： | 272420-007 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel386 EX Embedded Microprocessor |
| 中文描述： | 英特爾386防爆嵌入式微處理器 |
| 文件頁數(shù)： | 32/56頁 |
| 文件大?。?/td> | 766K |
| 代理商： | 272420-007 |
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Intel386 EX Embedded Microprocessor
32
Datasheet
Table 11. 5-Volt AC Characteristics (Sheet 1 of 5)
Symbol
Parameter
33 MHz
25 MHz
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
Operating Frequency
0
33
0
25
one-half CLK2 frequency
in MHz
(1)
t
1
t
2a
t
2b
t
3a
t
3b
t
4
t
5
t
6
t
7
t
8
t
8a
t
9
CLK2 Period
15
20
CLK2 High Time
6.25
7
(2)
CLK2 High Time
4
4
(2)
CLK2 Low Time
6.25
7
(2)
CLK2 Low Time
4.5
5
(2)
CLK2 Fall Time
4
7
(2)
CLK2 Rise Time
4
7
(2)
A25:1 Valid Delay
4
21
4
24
C
L
= 50 pF
(3)
A25:1 Float Delay
4
28
4
28
BHE#, BLE#, LOCK# Valid Delay
4
21
4
24
C
L
= 50 pF
C
L
= 50 pF
(3)
SMIACT# Valid Delay
4
21
4
24
BHE#, BLE#, LOCK# Float Delay
4
28
4
28
t
10
M/IO#, D/C#, W/R#, ADS#,
REFRESH# Valid Delay
4
21
4
24
C
L
= 50 pF
t
10a
RD#, WR# Valid Delay
4
18
4
22
t
10b
WR# Valid Delay for the rising
edge with respect to phase two
(external late READY#)
4
28
4
28
(6)
t
11
M/IO#, D/C#, W/R#, REFRESH#,
ADS# Float Delay
4
28
4
28
(3)
t
12
t
13
t
14
t
15
t
16
t
19
t
19a
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than I
LO
in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
D15:0 Write Data Valid Delay
4
23
4
23
C
L
= 50 pF
(3)
D15:0 Write Data Float delay
4
22
4
22
HLDA Valid Delay
4
18
4
22
C
L
= 50 pF
NA# Setup Time
5
5
NA# Hold Time
3
3
READY# Setup Time
8
9
BS8# Setup Time
11
11
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