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參數資料
| 型號： | ZR36504 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video & Audio Interface solution via USB |
| 中文描述： | 視頻 |
| 文件頁數： | 65/74頁 |
| 文件大?。?/td> | 298K |
| 代理商： | ZR36504 |
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
November-99
Page 65 of 65
9.
Programmable I/O Pins and 48MHz output pin
The ZR36504 has two programmable I/O pins for general purpose usage. These are IO-1
and IO-2 pins, which are Open-Drain.
Each of these pins - if used - must be connected to an external pull-up resistor to 3.3-5.0v
(if not used, it can be tied to GND). The external pull-up resistor should be in the range 1-
10K
.
To use these pins as inputs, the host computer should write '1' to the appropriate bit in the
IOPIN_REG register (in the ZR36504 register bank); these are IO_1 and IO_2 bits
respectively. In this condition, the voltage level presented on the IO-1 or IO-2 pin can be
read by the host computer via the appropriate bit ('0' represents <0.8v, '1' represents
>2.0v).
To use these pins as outputs, the host computer should write the output value to the
appropriate bit in the IOPIN_REG register; In this condition, and assuming that no external
device forces the voltage level presented on the IO-1 or IO-2 pin, the written value will be
reflected out ('0' will generate 0v, '1' will generate 3.3-5.0v).
Upon a Power On Reset or a USB-Reset operation, the IO-1 and IO-2 pins are cleared to
'0'. In the Suspend mode these pins are temporarily set to High-Z.
The ZR36504 can provide a 48MHz clock output for general purpose usage. The pin
CLK48 is dedicated for this usage, and is enabled when the CLK48_EN bit is set to '1'
(Reg.0/d3). When not enabled, the output level in this pin is constant '0'.
The 48MHz output is 50% duty cycle with 1nS jitter, and is derived from the external
12MHz crystal (an internal analog PLL is used).
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| ZR36730 | 制造商:ZORAN 制造商全稱:ZORAN 功能描述:INTEGRATED DVD DECODER |
| ZR36750 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Vaddis 5 (ZR36750) Product Brief |
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