
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
November-99
Page 31 of 31
Parameter
Register
address
Reg.27/d2-d0
VIN_REG1
Usage
VIN_MODE[2..0]
Video input mode:
000: 8-bit 4:2:2 mode, using synchronization pulses
001: 8-bit 4:2:2 mode, using CCIR 656 sync. codes
010: 16-bit 4:2:2 mode, using synchronization pulses
011: 16-bit 4:2:2 mode, using CCIR 656 sync. codes
100: 24-bit 4:4:4 mode, using synchronization pulses
110: 12-bit 4:1:1 mode, using synchronization pulses
101, 111: spare.
Polarity of VSNC pulse:
0: Synchronize on up-going edge
1: Synchronize on down-going edge
Polarity of HSNC pulse:
0: Synchronize on up-going edge
1: Synchronize on down-going edge
Polarity of FID (Field Identifier in Interlace mode) :
0: FID='0' during first (odd) field
1: FID='0' during second (even) field
Polarity of HVALID signal:
0: input signal HVALID='1' for active pixels
1: input signal HVALID='0' for active pixels
Polarity of VCLK (pixel clock):
0: Camera data valid at VCLK falling edge
1: Camera data valid at VCLK rising edge
0: Use external FID signal
1: Generate internal toggling FID. Ignore FID pin.
VSNC_POL
Reg.27/d3
VIN_REG1
HSNC_POL
Reg.27/d4
VIN_REG1
FID_POL
Reg.27/d5
VIN_REG1
HVALID_POL
Reg.27/d6
VIN_REG1
VCLK_POL
Reg.27/d7
VIN_REG1
AUTO_FID
Reg.28/d0
VIN_REG2
Reg.28/d1
VIN_REG2
Reg.28/d2
VIN_REG2
Reg.28/d3
VIN_REG2
Reg.28/d4
VIN_REG2
NON_INTERLACE
0: Interlace mode. Only even fields are transferred.
1: Non-interlace mode. All frames are transferred.
NO_HVALID
0: Normal operation
1: Ignore the HVALID input (assume constant '1')
UV_ID
0: Normal operation
1: Use V7 input as a U/V identifier ('1'=U, '0'=V)
FIX_2C
Fix 2's Compliment U/V values
0: Normal operation
1: Invert U[7] and V[7] to fix to Unsigned Binary
Number of pixels in active line of video source
XSIZE_IN[9..0]
Regs.29-30
LXSIZE_IN
MXSIZE_IN