參數(shù)資料
型號: ZR36504
廠商: Electronic Theatre Controls, Inc.
英文描述: Video & Audio Interface solution via USB
中文描述: 視頻
文件頁數(shù): 43/74頁
文件大?。?/td> 298K
代理商: ZR36504
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
November-99
Page 43 of 43
Reg.21/d7-d0 always '1' (end of a DRAM row). The bit a19 is
defined by DRM_COL_SLCT parameter.
Reg.19/d2,
Reg.22/d7-d0
buffer. Only a17..a9 are specified, the other 11
bits are always '0' (start of a DRAM row).
FDL_1ST_ROW
[8..0]
Start Address of Video Frame Delay Line
(continued...)
Parameter
Register
address
Reg.19/d7
Reg.19/d4-d3
Reg.23/d7-d0
Reg.24/d7-d0
Reg.18/d5
Reg.19/d5
Reg.25/d7-d0
Reg.18/d6
Reg.19/d6
Reg.26/d7-d0
Usage
FDL_LST_WORD
[18..0]
End Address of Video Frame Delay Line buffer.
VDW_1ST_ROW
[9..0]
Start Address of Video Output data buffer for
Write.
Normally
should
UR_1ST_ROW.
End Address of Video Output data buffer for
Write.
Normally
should
UR_LST_ROW.
be
equal
to
VDW_LST_ROW
[9..0]
be
equal
to
Register 18/d0 of the ZR36504 contains 3 bits named RES_UR, RES_FDL, and
RES_VDW. These are used to restart the appropriate FIFO pointers that are used for
DRAM access. The ZR36504 software driver is supposed to set these bits to '1' and then
to '0' if addresses of any of these buffers were modified.
The ZR36504 performs a Refresh cycle to DRAM from time to time. A special bit - REF -
in register 18 specifies the refresh time for the whole address space. This allows the user to
use either a 8.2ms refresh chip or a 128ms one (Selecting 8.2ms mode will fit both 4M and
16M DRAM types).
DRAM Interface Signals
The following signals are used by the ZR36504 for DRAM access:
DA[9..0]:
Address-Bus, multiplexed Row address and Column address.
If a 4Mbit DRAM is used, DA[9] should be left open.
DD[15..0]:
Data-Bus, bi-directional bus with internal pull-down.
RASN:
Raw-Address Select (active Low).
CASN:
Column-Address Select (active Low. Can drive two DRAM pins).
WRN:
Write Enable signal (active Low).
OEN:
Read Enable signal (active Low).
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